公开(公告)号：US07612585B2

公开(公告)日：2009-11-03

申请号：US11654445

申请日：2007-01-17

申请人： Pulkit Shah ,  Prasad Kotra

发明人： Pulkit Shah ,  Prasad Kotra

IPC分类号： H03K19/094

CPC分类号： H03K5/08

摘要： An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

摘要翻译： 输入缓冲器具有与低电压脚并联的高电压脚。 当焊盘电压低于电源电压时，低压脚拉起焊盘。 当焊盘电压低于电源时，高压脚保持关闭。 当焊盘电压高于电源电压时，低压脚断开。 当焊盘电压高于电源电压时，高压端子接通。 当焊盘电压高于电源电压时，低压偏置电路和高压偏置电路保护低压和低压端的晶体管。 因此，上拉电路具有高耐压性，并且不会从焊盘吸收电流。

公开(公告)号：US20070164804A1

公开(公告)日：2007-07-19

申请号：US11654445

申请日：2007-01-17

申请人： Pulkit Shah ,  Prasad Kotra

发明人： Pulkit Shah ,  Prasad Kotra

IPC分类号： H03K5/08

CPC分类号： H03K5/08

摘要： An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

摘要翻译： 输入缓冲器具有与低电压脚并联的高电压脚。 当焊盘电压低于电源电压时，低压脚拉起焊盘。 当焊盘电压低于电源时，高压脚保持关闭。 当焊盘电压高于电源电压时，低压脚断开。 当焊盘电压高于电源电压时，高压端子接通。 当焊盘电压高于电源电压时，低压偏置电路和高压偏置电路保护低压和低压端的晶体管。 因此，上拉电路具有高耐压性，并且不会从焊盘吸收电流。

公开(公告)号：US07598812B2

公开(公告)日：2009-10-06

申请号：US11818172

申请日：2007-06-12

申请人： Pulkit Shah ,  Gajender Rohilla

发明人： Pulkit Shah ,  Gajender Rohilla

IPC分类号： H03F3/08

CPC分类号： H03F3/08 ,  H03F1/52

摘要： A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.

摘要翻译： 一种用于放大器电路的短路输入检测的方法和装置。 电路的实施例包括多个放大器电路，每个放大器电路具有输入和输出。 该电路还包括多个短路检测电路，其中一个短路检测电路耦合到每个放大器电路的输入端。 每个短路检测电路具有用于检测短路的有效状态和用于正常放大器操作的无效状态。 电路还包括与每个放大器电路的输出耦合的寄存器，以保持一个或多个放大器电路的输出。

公开(公告)号：US06933786B1

公开(公告)日：2005-08-23

申请号：US10146524

申请日：2002-05-15

申请人： Palathol mana Sivadasan Mohandas ,  Gajender Rohilla ,  Pulkit Shah

发明人： Palathol mana Sivadasan Mohandas ,  Gajender Rohilla ,  Pulkit Shah

IPC分类号： H03F1/56 ,  H03F3/08 ,  H03F3/45 ,  H03G1/00

CPC分类号： H03F1/56 ,  H03F3/08 ,  H03F3/087 ,  H03F3/45085 ,  H03F3/45475 ,  H03F2200/222 ,  H03F2203/45702 ,  H03G1/007 ,  H03G1/0088

摘要： An amplifier system has a control circuit. An amplifier is coupled to the control circuit and has a controllable gain. A controllable input impedance circuit is coupled to the control circuit. When the gain of the amplifier is changed the controllable input impedance circuit's impedance is adjusted, so that the input impedance to the system remains essentially constant.

摘要翻译： 放大器系统具有控制电路。 放大器耦合到控制电路并具有可控增益。 可控输入阻抗电路耦合到控制电路。 当放大器的增益改变时，调节可控输入阻抗电路的阻抗，使得系统的输入阻抗基本保持恒定。

公开(公告)号：US08711096B1

公开(公告)日：2014-04-29

申请号：US12413354

申请日：2009-03-27

申请人： Ke-Cai Zeng ,  Jonathan Young ,  Pulkit Shah ,  Yansun Xu ,  Eric Mann ,  Shankar Subramani

发明人： Ke-Cai Zeng ,  Jonathan Young ,  Pulkit Shah ,  Yansun Xu ,  Eric Mann ,  Shankar Subramani

IPC分类号： G06F3/033

CPC分类号： G06F3/03543 ,  G06F1/263 ,  G06F3/0317 ,  G06F3/038

摘要： A dual protocol input device for use with a host system is provided. In one embodiment, the input device comprises a chip with a number of semiconductor devices integrally formed thereon, including: an optical navigation sensor (ONS) to sense movement of the ONS relative to a surface; a wired protocol block to communicate data from the ONS to the host system by a wired communication protocol; a wireless protocol block to communicate data from the ONS to the host system by a wireless communication protocol; and a micro-controller coupled to the ONS, the wired protocol block and the wireless protocol block, to switch the input device between the wireless communication protocol and the wired communication protocol.

摘要翻译： 提供了一种与主机系统一起使用的双协议输入设备。 在一个实施例中，所述输入装置包括其上整体形成有多个半导体器件的芯片，包括：用于感测所述ONS相对于表面的移动的光学导航传感器（ONS） 有线协议块，用于通过有线通信协议将数据从ONS传送到主机系统; 无线协议块，用于通过无线通信协议将数据从ONS传送到主机系统; 以及耦合到ONS的微控制器，有线协议块和无线协议块，以在无线通信协议和有线通信协议之间切换输入设备。

公开(公告)号：US08174291B1

公开(公告)日：2012-05-08

申请号：US10875888

申请日：2004-06-24

申请人： Pulkit Shah ,  Gajendar Rohilla

发明人： Pulkit Shah ,  Gajendar Rohilla

IPC分类号： H03K5/22

CPC分类号： H03K5/1565

摘要： An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively. In this manner, the method provides an output signal with an output duty cycle that is substantially equal to the input duty cycle.

摘要翻译： 本文提供了一种用于在缓冲电路的输入和输出信号之间最小化（或完全消除）占空比失真的改进的缓冲电路和方法。 通常，改进的缓冲电路基本上将缓冲电路的充电和放电电流路径与提供给缓冲电路的参考电压相分离。 这确保输入和输出信号的上升沿和下降沿之间的时间延迟基本上相等，从而即使当参考电压接近晶体管阈值电压时，减小占空比失真并保持缓冲电路的最大工作频率。 此外，改进的方法可以包括将具有输入占空比的输入信号转发到一对下拉晶体管的相互连接的栅极端子上，以及在逻辑高电平期间激活/去激活一对下拉晶体管中的至少一个，以及 输入占空比的逻辑低电压值。 以这种方式，该方法提供具有基本上等于输入占空比的输出占空比的输出信号。

公开(公告)号：US07809035B2

公开(公告)日：2010-10-05

申请号：US11432987

申请日：2006-05-12

申请人： Steven Sanders ,  Gary Gibbs ,  Ashish Pancholy ,  Gajender Rohilla ,  Pulkit Shah

发明人： Steven Sanders ,  Gary Gibbs ,  Ashish Pancholy ,  Gajender Rohilla ,  Pulkit Shah

IPC分类号： H01S3/00

CPC分类号： H01S5/042 ,  H01S5/06808

摘要： The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. A first current limiter circuit configured to limit a current output from the current source to an anode of the diode laser, and an independent second current limiter circuit configured to limit a current return from a cathode of the diode laser to the current source so that laser output power does not exceed a specified maximum regardless of a single fault in either the first or second current limiter circuits.

摘要翻译： 该装置包括二极管激光器和与二极管激光器互连的电流源。 电流源中的两个独立电路被配置为限制流过二极管激光器的电流。 第一限流器电路，被配置为将来自电流源的电流输出限制到二极管激光器的阳极;以及独立的第二限流器电路，其被配置为限制从二极管激光器的阴极到电流源的电流返回，使得激光器 输出功率不超过规定的最大值，而与第一或第二限流器电路中的单个故障无关。

公开(公告)号：US07755348B1

公开(公告)日：2010-07-13

申请号：US12413559

申请日：2009-03-28

申请人： Pulkit Shah ,  Gajender Rohilla

发明人： Pulkit Shah ,  Gajender Rohilla

IPC分类号： G01R1/30

CPC分类号： G01R35/005 ,  G01R19/0092

摘要： Analog channel calibration methods, devices and systems are disclosed. One embodiment of the present invention pertains to a method for calibrating a channel offset of a current sensor which comprises measuring a channel offset native to a current sensor channel. The method also comprises storing the channel offset native to the current sensor channel to a register associated with the current sensor channel as a value. Additionally, the method comprises calibrating an output signal generated in response to an input signal to the current sensor channel based on the value.

摘要翻译： 公开了模拟通道校准方法，装置和系统。 本发明的一个实施例涉及一种用于校准电流传感器的通道偏移的方法，其包括测量对当前传感器通道原生的通道偏移。 该方法还包括将当前传感器信道的原始信道偏移量存储到与当前传感器信道相关联的寄存器中作为值。 另外，该方法包括基于该值来校准响应于当前传感器通道的输入信号而产生的输出信号。

公开(公告)号：US20080001676A1

公开(公告)日：2008-01-03

申请号：US11818172

申请日：2007-06-12

申请人： Pulkit Shah ,  Gajender Rohilla

发明人： Pulkit Shah ,  Gajender Rohilla

IPC分类号： H03F3/08

CPC分类号： H03F3/08 ,  H03F1/52

摘要： A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.

摘要翻译： 一种用于放大器电路的短路输入检测的方法和装置。 电路的实施例包括多个放大器电路，每个放大器电路具有输入和输出。 该电路还包括多个短路检测电路，其中一个短路检测电路耦合到每个放大器电路的输入端。 每个短路检测电路具有用于检测短路的有效状态和用于正常放大器操作的无效状态。 电路还包括与每个放大器电路的输出耦合的寄存器，以保持一个或多个放大器电路的输出。

公开(公告)号：US20070230525A1

公开(公告)日：2007-10-04

申请号：US11432987

申请日：2006-05-12

申请人： Steven Sanders ,  Gary Gibbs ,  Ashish Pancholy ,  Gajender Rohilla ,  Pulkit Shah

发明人： Steven Sanders ,  Gary Gibbs ,  Ashish Pancholy ,  Gajender Rohilla ,  Pulkit Shah

IPC分类号： H01S3/00

CPC分类号： H01S5/042 ,  H01S5/06808

摘要： One embodiment relates to an optical navigation apparatus which provides fault-tolerant limitation of laser output power. The apparatus includes a diode laser and a current source interconnected with the diode laser. Two independent circuits in the current source are configured to limit current flowing through the diode laser. Another embodiment relates to a method of providing fault-tolerant limitation of laser output power in an optical navigation apparatus. A first digital current limit value is converted to a first analog signal, and the first analog signal is used to limit an electrical current from a power supply connection to an anode of a diode laser. A second digital current limit value is converted to a second analog signal, and the second analog signal is used to limit an electrical current from a cathode of the diode laser to a ground connection. Other embodiments are also disclosed.

摘要翻译： 一个实施例涉及提供激光输出功率的容错限制的光学导航装置。 该装置包括二极管激光器和与二极管激光器互连的电流源。 电流源中的两个独立电路被配置为限制流过二极管激光器的电流。 另一实施例涉及在光学导航装置中提供激光输出功率的容错限制的方法。 第一数字电流限制值被转换为第一模拟信号，并且第一模拟信号用于限制从二极管激光器的电源连接到电源连接的电流。 第二数字电流限制值被转换为第二模拟信号，并且第二模拟信号用于限制从二极管激光器的阴极到接地连接的电流。 还公开了其他实施例。