Invention Application
US20070176240A1 WAFER LEVEL PACKAGE HAVING FLOATED METAL LINE AND METHOD THEREOF
有权
具有浮选金属线的水平包装及其方法
- Patent Title: WAFER LEVEL PACKAGE HAVING FLOATED METAL LINE AND METHOD THEREOF
- Patent Title (中): 具有浮选金属线的水平包装及其方法
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Application No.: US11556931Application Date: 2006-11-06
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Publication No.: US20070176240A1Publication Date: 2007-08-02
- Inventor: Hyun-soo Chung , Seung-duk Baek , Ju-il Choi , Dong-ho Lee
- Applicant: Hyun-soo Chung , Seung-duk Baek , Ju-il Choi , Dong-ho Lee
- Priority: KR10-2006-0009062 20060127
- Main IPC: H01L23/62
- IPC: H01L23/62
Abstract:
A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.
Public/Granted literature
- US07767576B2 Wafer level package having floated metal line and method thereof Public/Granted day:2010-08-03
Information query
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