发明申请
US20070178692A1 MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION 有权
形成用于铜层形成的障壁膜的多步法

MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
摘要:
Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer followed by bulk copper-containing layer formation. The substrate is annealed to form a final barrier layer. In a related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer. In yet another related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.
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IPC分类:
H 电学
H01 基本电气元件
H01L 半导体器件;其他类目中不包括的电固体器件(使用半导体器件的测量入G01;一般电阻器入H01C;磁体、电感器、变压器入H01F;一般电容器入H01G;电解型器件入H01G9/00;电池组、蓄电池入H01M;波导管、谐振器或波导型线路入H01P;线路连接器、汇流器入H01R;受激发射器件入H01S;机电谐振器入H03H;扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R;一般电光源入H05B;印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K;在具有特殊应用的电路中使用的半导体器件见应用相关的小类)
H01L21/00 专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02 .半导体器件或其部件的制造或处理
H01L21/04 ..至少具有一个跃变势垒或表面势垒的器件,例如PN结、耗尽层、载体集结层
H01L21/34 ...具有H01L21/06,H01L21/16及H01L21/18各组不包含的或有或无杂质,例如掺杂材料的半导体的器件
H01L21/46 ....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的(在半导体材料上制作电极的入H01L21/44)
H01L21/461 .....改变半导体材料的表面物理特性或形状的,例如腐蚀、抛光、切割
H01L21/4763 ......非绝缘层的沉积,例如绝缘层上的导电层、电阻层;这些层的后处理(电极的制造入H01L21/28)
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