公开(公告)号：US20070178692A1

公开(公告)日：2007-08-02

申请号：US11733673

申请日：2007-04-10

申请人： Wilbur Catabay ,  Zhihai Wang ,  Ping Li

发明人： Wilbur Catabay ,  Zhihai Wang ,  Ping Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization. Other embodiments include providing a substrate in a processing chamber and forming a copper seed layer on the substrate. The seed layer is implanted with barrier materials to form an implanted seed layer followed by bulk copper-containing layer formation. The substrate is annealed to form a final barrier layer. In a related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a copper seed layer on the first barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer. In yet another related embodiment the step of forming a seed layer is replaced with the steps of forming a first barrier layer on the substrate and forming a second barrier layer on the first layer. A copper seed layer is formed on the second barrier layer. After implantation of barrier material into the seed layer and bulk deposition of copper-containing material, the substrate is annealed to form a final barrier layer.

摘要翻译： 本发明的实施例包括一种形成具有双层铜阻挡层的铜互连的方法。 该方法包括以下步骤：在处理室中提供衬底，所述衬底具有低K电介质绝缘层和绝缘层中的开口。 在绝缘层和开口中形成钽/氮化钽的第一阻挡层。 在第一阻挡层上形成第二阻挡层。 第二阻挡层由选自钯，铬，钽，镁和钼的材料组成。 在第二阻挡层上形成铜籽晶层，在籽晶层上形成体铜层。 将衬底退火并进行可包括平坦化的进一步加工。 其他实施例包括在处理室中提供衬底并在衬底上形成铜籽晶层。 种子层被植入阻挡材料以形成植入的种子层，然后形成大块含铜层。 将衬底退火以形成最终的阻挡层。 在相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一阻挡层上形成铜籽晶层的步骤。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。 在另一相关实施例中，形成种子层的步骤被替换为在衬底上形成第一阻挡层并在第一层上形成第二阻挡层的步骤。 在第二阻挡层上形成铜籽晶层。 在将阻挡材料植入种子层和含铜材料的大量沉积之后，将衬底退火以形成最终的阻挡层。

公开(公告)号：US06204550B1

公开(公告)日：2001-03-20

申请号：US09251702

申请日：1999-02-17

申请人： Zhihai Wang ,  Wei-Jen Hsia ,  Wilbur Catabay

发明人： Zhihai Wang ,  Wei-Jen Hsia ,  Wilbur Catabay

IPC分类号： H01L23495

CPC分类号： H01L21/02071 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844

摘要： Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

摘要翻译： 提供了用于RF溅射清洗接触孔和通孔的方法和组合物，其在孔中提供基本上均匀的电荷分布并使电子阴影最小化。 这通过诸如PVD的各向同性地沉积在围绕孔的晶片表面和孔的侧面的导电材料层来实现。 各向同性沉积使得在高纵横比下，沟槽和孔沉积在顶部最重，底部最小（由于沉积阴影效应）。 沉积的导电材料优选是在沉积插塞材料之前也用作孔中的衬垫的金属。 导电材料提供用于负电荷的路径，否则在RF溅射清洗期间积聚在孔的顶部以到达孔的底部，从而防止在孔内和周围累积一个极性的电荷。 因此，如上所述，通过常规RF溅射引起的栅极氧化物上的应力得以缓解。

公开(公告)号：US5994211A

公开(公告)日：1999-11-30

申请号：US976033

申请日：1997-11-21

申请人： Zhihai Wang ,  Wei-Jen Hsia ,  Wilbur Catabay

发明人： Zhihai Wang ,  Wei-Jen Hsia ,  Wilbur Catabay

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/70

CPC分类号： H01L21/02071 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844

摘要： Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

摘要翻译： 提供了用于RF溅射清洗接触孔和通孔的方法和组合物，其在孔中提供基本上均匀的电荷分布并使电子阴影最小化。 这通过诸如PVD的各向同性地沉积在围绕孔的晶片表面和孔的侧面的导电材料层来实现。 各向同性沉积使得在高纵横比下，沟槽和孔沉积在顶部最重，底部最小（由于沉积阴影效应）。 沉积的导电材料优选是在沉积插塞材料之前也用作孔中的衬垫的金属。 导电材料提供用于负电荷的路径，否则在RF溅射清洗期间积聚在孔的顶部以到达孔的底部，从而防止在孔内和周围累积一种极性的电荷。 因此，如上所述，通过常规RF溅射引起的栅极氧化物上的应力得以缓解。

公开(公告)号：US20060035457A1

公开(公告)日：2006-02-16

申请号：US10915166

申请日：2004-08-10

申请人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Richard Carter ,  Peter Burke ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837

摘要： An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

摘要翻译： 对集成电路的制造方法的改进。 移除横向围绕导电互连的所有电介质材料，同时留下直接位于导电互连之下的电介质材料。 导电互连件用低k材料填充，其中低k材料在横向相邻的导电互连之间提供低电容，并且导电互连件下面的剩余电介质材料为导电互连提供结构支撑。

公开(公告)号：US20060035455A1

公开(公告)日：2006-02-16

申请号：US10915719

申请日：2004-08-10

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

公开(公告)号：US20060118523A1

公开(公告)日：2006-06-08

申请号：US11337460

申请日：2006-01-23

申请人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

发明人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

IPC分类号： B44C1/22 ,  C23F1/00 ,  C03C15/00

CPC分类号： B23H5/08 ,  C23F1/02 ,  C23F4/00 ,  C25F3/02 ,  H01L21/02063 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/7684

摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

摘要翻译： 在衬底上形成平坦化层的方法，其中衬底被清洁，并且形成具有高部分和低部分的表面的层。 电阻掩模形成在层的低部分上，但不在层的高部分之上。 蚀刻层的表面，其中层的高部分暴露于蚀刻，但是电阻掩模下面的层的低部分不暴露于蚀刻。 层的表面的蚀刻继续进行直到层的高部分与层的低部分基本相同的水平，从而提供层的表面的初始平坦化。 电阻掩模从层的表面去除，并且层的所有表面被平坦化以提供平坦化层。

公开(公告)号：US20080308937A1

公开(公告)日：2008-12-18

申请号：US12138595

申请日：2008-06-13

申请人： Wilbur Catabay ,  Julian Searle ,  Wei-Jen Hsia ,  Milan Prejda ,  Rohini Ranganathan ,  Lahcene Smati ,  Majid Milani

发明人： Wilbur Catabay ,  Julian Searle ,  Wei-Jen Hsia ,  Milan Prejda ,  Rohini Ranganathan ,  Lahcene Smati ,  Majid Milani

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.

摘要翻译： 本文提供了无铜半导体器件界面的实施例以及用于形成和/或利用其的方法。 在一些实施例中，半导体结构可以包括具有暴露的含铜特征的衬底; 以及设置在衬底上方的无铜界面，并且在含铜特征和无铜界面的上表面之间提供导电互连，以便于将衬底电耦合到半导体器件，同时将半导体器件与 含铜功能。

公开(公告)号：US20070163993A1

公开(公告)日：2007-07-19

申请号：US11695169

申请日：2007-04-02

申请人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

发明人： Wilbur Catabay ,  Wei-Jen Hsia ,  Hao Cui

IPC分类号： C23F1/00 ,  B44C1/22 ,  C03C15/00

CPC分类号： B23H5/08 ,  C23F1/02 ,  C23F4/00 ,  C25F3/02 ,  H01L21/02063 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/7684

摘要： A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

公开(公告)号：US20060118919A1

公开(公告)日：2006-06-08

申请号：US11007392

申请日：2004-12-07

申请人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

发明人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

IPC分类号： H01L29/04

CPC分类号： H01L29/51 ,  C23C14/226 ,  C23C14/3442 ,  C23C14/46 ,  C23C16/486 ,  H01L21/02189 ,  H01L21/02266 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645

摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

公开(公告)号：US20070190784A1

公开(公告)日：2007-08-16

申请号：US11736402

申请日：2007-04-17

申请人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

发明人： Hao Cui ,  Peter Burke ,  Wilbur Catabay

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76883

摘要： Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack.

摘要翻译： 本发明的实施例包括具有增加的电迁移寿命的铜互连结构。 这种结构可以包括其上形成有铜层的半导体衬底。 在铜层上形成介电阻挡层叠体。 电介质势垒叠层包括邻近铜层形成的第一部分和形成在第一部分上的第二部分，第一部分具有相对于第二部分具有改进的铜的粘合性，并且两个部分形成为具有耐铜扩散性。 本发明还包括用于构造这种结构的几个实施例。 可以通过等离子体处理或离子注入电介质阻挡层的选定部分与粘合增强材料来增加电介质阻挡层与铜的附着，以增加堆叠中这种材料的浓度。