发明申请
- 专利标题： Reconfigurable logic block, programmable logic device provided with the reconfigurable logic block, and method of fabricating the reconfigurable logic block
- 专利标题（中）： 可配置逻辑块，可配置逻辑块的可编程逻辑器件，以及制造可重构逻辑块的方法
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申请号： US11598679申请日： 2006-11-14
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公开(公告)号： US20070186203A1公开(公告)日： 2007-08-09
- 发明人: Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
- 申请人： Toshinori Sueyoshi , Masahiro Iida , Motoki Amagasaki , Kazuhiko Taketa , Taketo Heishi , Nobuharu Suzuki
- 申请人地址： JP Yokohama
- 专利权人： SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
- 当前专利权人： SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
- 当前专利权人地址： JP Yokohama
- 优先权： JP2005-330268 20051115; JP2006-166387 20060615
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H03K17/693
摘要：
A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.