公开(公告)号：US08963124B2

公开(公告)日：2015-02-24

申请号：US12405505

申请日：2009-03-17

申请人： Masanobu Miyao ,  Hiroshi Nakashima ,  Taizoh Sadoh ,  Ichiro Mizushima ,  Masaki Yoshimaru

发明人： Masanobu Miyao ,  Hiroshi Nakashima ,  Taizoh Sadoh ,  Ichiro Mizushima ,  Masaki Yoshimaru

IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L27/06 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L27/0617 ,  H01L21/02672 ,  H01L29/66984

摘要： At least first and second Si1-xGex (0≦x≦1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0≦x≦1) layers. A lattice constant of the first Si1-xGex (0≦x≦1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0≦x≦1) layer is matched with a lattice constant of the second material layer.

摘要翻译： 在绝缘膜上形成至少第一和第二Si1-xGex（0＆nlE; x＆lt; 1; 1）层。 至少第一和第二材料层对应于至少第一和第二Si1-xGex（0＆amp; n1; x＆amp; l1; 1）层形成。 第一Si1-xGex（0＆nlE; x＆nlE; 1）层的晶格常数与第一材料层的晶格常数相匹配。 第二Si1-xGex（0＆nlE; x＆nlE; 1）层的晶格常数与第二材料层的晶格常数相匹配。

公开(公告)号：US08941524B2

公开(公告)日：2015-01-27

申请号：US13874531

申请日：2013-05-01

申请人： Semiconductor Technology Academic Research Center

发明人： Hiroshi Kawaguchi ,  Masahiko Yoshimoto ,  Toshihiro Konishi ,  Shintaro Izumi ,  Keisuke Okuno

IPC分类号： H03M1/50 ,  G04F10/00

CPC分类号： H03M1/50 ,  G04F10/005

摘要： A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.

摘要翻译： 提供了一种TD转换器，用于将延迟时间值数字转换为数字值。 在TD转换器中，振荡器电路部分输入时域数据。 当时域数据处于第一状态时，第一状态计数器电路部分测量来自振荡器电路部分的输出振荡波形的波数，并且第二状态计数器电路部分测量输出振荡波形的波数 当时域数据处于第二状态时，来自振荡器电路部分。 输出信号发生器部分基于第一状态计数器电路部分和第二状态计数器电路部分的输出计数值产生输出信号，并且频率控制电路控制振荡器电路部分总是振荡并控制振荡频率 的振荡器电路部分。

公开(公告)号：US08709939B2

公开(公告)日：2014-04-29

申请号：US13633562

申请日：2012-10-02

申请人： Semiconductor Technology Academic Research Center ,  National University Corporation Tohoku University

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L21/4763

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 描述了半导体器件中的多层互连结构及其制造方法。 半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层，形成在第一绝缘层上的Cu互连层，形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层 在Cu互连层和第二绝缘层之间。 金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理而形成。

公开(公告)号：US08692701B2

公开(公告)日：2014-04-08

申请号：US13599195

申请日：2012-08-30

申请人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

发明人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

IPC分类号： H03M1/38

CPC分类号： H03M1/06 ,  H03M1/167

摘要： A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

摘要翻译： 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容进行采样，保持和放大输入信号。

公开(公告)号：US08614570B2

公开(公告)日：2013-12-24

申请号：US13192854

申请日：2011-07-28

申请人： Tetsuya Hirose ,  Yuji Osaki

发明人： Tetsuya Hirose ,  Yuji Osaki

IPC分类号： G05F3/16 ,  G05F1/10

CPC分类号： G05F3/242

摘要： A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.

摘要翻译： MOS晶体管基于在漏极及其源极上感应的电压产生输出电流。 栅极偏置电压发生器电路产生栅极偏置电压，以便在强反转线性区域中操作MOS晶体管，并且将栅极偏置电压施加到MOS晶体管的栅极。 漏极偏置电压发生器电路产生漏极偏置电压，并将漏极偏置电压施加到MOS晶体管的漏极。 添加的偏置电压发生器电路产生具有预定温度系数并且包括预定偏移电压的附加偏置电压，使得输出电流随着温度变化而变得恒定。 漏极偏置电压发生器电路将添加的偏置电压加到漏极偏置电压，并将加法结果的电压作为漏极偏置电压施加到MOS晶体管的漏极。

公开(公告)号：US08436654B2

公开(公告)日：2013-05-07

申请号：US13181825

申请日：2011-07-13

申请人： Tetsuya Hirose ,  Yuji Osaki ,  Toshihiko Mori

发明人： Tetsuya Hirose ,  Yuji Osaki ,  Toshihiko Mori

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

摘要翻译： 提供电平转换器电路，用于将具有第一信号电平的数字信号的输入信号转换为具有高于第一信号电平的第二信号电平的输出信号。 放大器电路放大输入信号并输出​​放大的输出信号，并且电流发生器电路在输入信号的信号电平改变时产生对应于流过放大器电路的工作电流的控制电流。 电流检测器电路检测所产生的控制电流，并且控制放大器电路的工作电流对应于检测到的控制电流。 电流发生器电路包括插入电流检测器电路和地之间的串联连接的第一和第二nMOS晶体管。 第一nMOS晶体管响应于输入信号而工作，并且第二nMOS晶体管响应输入信号的反相信号而工作。

公开(公告)号：US20120314486A1

公开(公告)日：2012-12-13

申请号：US13492231

申请日：2012-06-08

申请人： Masahiko YOSHIMOTO ,  Hiroshi KAWAGUCHI ,  Shunsuke YOSHIMOTO

发明人： Masahiko YOSHIMOTO ,  Hiroshi KAWAGUCHI ,  Shunsuke YOSHIMOTO

IPC分类号： G11C11/00

CPC分类号： G11C11/419

摘要： It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines.

摘要翻译： 旨在提供一种能够解决8Tr SRAM中的半选择问题的半导体存储器件，并且同时实现半选择列中的充电/放电功率的降低，这已经是常规回写的问题 方案。 8Tr SRAM包括1）位线半驱动器电路，其能够从列方向读取存储器单元组的每个存储单元的读位线（RBL）读取保留数据，并仅驱动一半的存储单元的写位线 - 根据读取的数据选择的列; 2）选择信号电路，其中输入有位线半驱动电路的使能信号和列选择信号，并且激活位线半驱动电路;以及3）均衡器电路 在列方向上写存储单元组的位线，并且不预写写位线。

公开(公告)号：US08305134B2

公开(公告)日：2012-11-06

申请号：US12713362

申请日：2010-02-26

申请人： Tetsuya Hirose ,  Toyoaki Kito ,  Yuji Osaki

发明人： Tetsuya Hirose ,  Toyoaki Kito ,  Yuji Osaki

IPC分类号： G05F1/10

CPC分类号： G05F3/242

摘要： A reference current source circuit outputs a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current.

摘要翻译： 参考电流源电路输出恒定的参考电流，即使在诸如温度和电源电压的周围环境中，在以毫安量级的微小电流区域中操作的电源电路中也会发生变化。 参考电流源电路包括nMOS配置的电源电路，pMOS配置的电源电路和电流减法器电路。 nMOS配置的电源电路包括电流产生nMOSFET，并且产生具有取决于电子迁移率的输出电流的温度特性的第一电流。 pMOS配置的电源电路包括电流产生pMOSFET，并且产生具有取决于空穴迁移率的输出电流的温度特性的第二电流。 电流减法器电路通过从第一电流中减去第二电流来产生恒定的参考电流。

公开(公告)号：US20120182064A1

公开(公告)日：2012-07-19

申请号：US13377009

申请日：2010-06-11

申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

IPC分类号： G05F1/10

CPC分类号： G11C11/413

摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极和半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

公开(公告)号：US08144045B2

公开(公告)日：2012-03-27

申请号：US12828641

申请日：2010-07-01

申请人： Makoto Nagata ,  Takushi Hashida

发明人： Makoto Nagata ,  Takushi Hashida

IPC分类号： H03M1/82

CPC分类号： H03K5/2472 ,  G01R31/31922

摘要： A timing signal generator circuit includes a DA converter converting an input digital value into an analog voltage, and a VT converter converting the analog voltage into a corresponding delay time. The DA converter includes a current source circuit, which supplies a current (n×Is) (“n” is a number corresponding to the input digital value) selected from a total supply current (N×Is) as a current Iout to the resistors, and supplies the remaining current (N−n)×Is as a current Idump to the resistors, outputs a voltage across the resistors as an analog voltage Vdac, and outputs a voltage across the resistor as a reset voltage Vreset. The VT converter charges the integration capacitor with a constant current from the constant current source by using the reset voltage as an initial voltage, and outputs a timing signal when the integral voltage exceeds the analog voltage.

摘要翻译： 定时信号发生器电路包括将输入数字值转换为模拟电压的DA转换器和将模拟电压转换为相应的延迟时间的VT转换器。 DA转换器包括电流源电路，其将从总供电电流（N×Is）中选择的电流（n×Is）（“n”为与输入数字值对应的数字）作为电流Iout提供给电阻器 ，并将剩余电流（N-n）×Is作为当前Idump提供给电阻器，将电阻器两端的电压作为模拟电压Vdac输出，并将电阻两端的电压输出为复位电压Vreset。 VT转换器通过使用复位电压作为初始电压从恒流源以恒定电流对积分电容器充电，当积分电压超过模拟电压时，输出定时信号。