Invention Application
US20070204248A1 Delay analyzing method, delay analyzing apparatus, and computer product
有权
延迟分析方法,延迟分析仪器和计算机产品
- Patent Title: Delay analyzing method, delay analyzing apparatus, and computer product
- Patent Title (中): 延迟分析方法,延迟分析仪器和计算机产品
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Application No.: US11521138Application Date: 2006-09-14
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Publication No.: US20070204248A1Publication Date: 2007-08-30
- Inventor: Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
- Applicant: Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Priority: JP2006-052430 20060228
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
Public/Granted literature
- US07516432B2 Circuit delay analyzing method, circuit delay analyzing apparatus, and computer product Public/Granted day:2009-04-07
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