发明申请
US20070204248A1 Delay analyzing method, delay analyzing apparatus, and computer product
有权
延迟分析方法,延迟分析仪器和计算机产品
- 专利标题: Delay analyzing method, delay analyzing apparatus, and computer product
- 专利标题(中): 延迟分析方法,延迟分析仪器和计算机产品
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申请号: US11521138申请日: 2006-09-14
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公开(公告)号: US20070204248A1公开(公告)日: 2007-08-30
- 发明人: Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
- 申请人: Katsumi Homma , Toshiyuki Shibuya , Hidetoshi Matsuoka , Izumi Nitta
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 优先权: JP2006-052430 20060228
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.
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