公开(公告)号：US08799841B2

公开(公告)日：2014-08-05

申请号：US13434598

申请日：2012-03-29

申请人： Subodh M. Reddy ,  Toshiyuki Shibuya

发明人： Subodh M. Reddy ,  Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/08

摘要： According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components.

摘要翻译： 根据实施例的一个方面，设计模拟电路的方法可以包括为电路选择多个模拟分量。 该方法还可以包括对模拟组件进行排序。 该方法还可以包括为每个模拟分量的参数确定至少一个帕累托最优设计点。 每个模拟组件的帕累托最优设计点可以基于性能度量，相应模拟组件的参数以及由模拟量排序中的相应模拟组件之前的模拟组件的帕累托最优设计点产生的约束 组件。

公开(公告)号：US08751999B2

公开(公告)日：2014-06-10

申请号：US13176310

申请日：2011-07-05

申请人： Toshiyuki Shibuya

发明人： Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.

摘要翻译： 在一个实施例中，通过在PCB上分别在n个位置创建n个边界线并分别在n个边界线上放置n组电子部件来为印刷电路板（PCB）创建布局; 并迭代地调整和评估PCB的布局，直到满足PCB的布局要求为止。

公开(公告)号：US20130014076A1

公开(公告)日：2013-01-10

申请号：US13176310

申请日：2011-07-05

申请人： Toshiyuki Shibuya

发明人： Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： In one embodiment, creating a layout for a Printed Circuit Board (PCB) by creating n boundary lines at n locations, respectively, on the PCB and placing n sets of electronic components on the n boundary lines, respectively; and iteratively adjusting and evaluating the layout of the PCB until a set of layout requirements for the PCB has been satisfied.

摘要翻译： 在一个实施例中，通过在PCB上分别在n个位置创建n个边界线并分别在n个边界线上放置n组电子部件来为印刷电路板（PCB）创建布局; 并迭代地调整和评估PCB的布局，直到满足PCB的布局要求为止。

公开(公告)号：US07934182B2

公开(公告)日：2011-04-26

申请号：US12193431

申请日：2008-08-18

申请人： Izumi Nitta ,  Katsumi Homma ,  Toshiyuki Shibuya

发明人： Izumi Nitta ,  Katsumi Homma ,  Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.

摘要翻译： 通过输入多个信号的节点并且预测统计MAX中的估计为大的部分路径的延迟分布，其存在于对电路延迟有很大影响的关键路径上， 并且具有改善电路延迟的可能性很高，通过蒙特卡罗模拟而不是基于块的仿真来计算电路图中的节点，从而提高延迟分析的速度和精度。

公开(公告)号：US20090138838A1

公开(公告)日：2009-05-28

申请号：US12193431

申请日：2008-08-18

申请人： Izumi Nitta ,  Katsumi Homma ,  Toshiyuki Shibuya

发明人： Izumi Nitta ,  Katsumi Homma ,  Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.

摘要翻译： 通过输入多个信号的节点并且预测统计MAX中的估计为大的部分路径的延迟分布，其存在于对电路延迟有很大影响的关键路径上， 并且具有改善电路延迟的可能性很高，通过蒙特卡罗模拟而不是基于块的仿真来计算电路图中的节点，从而提高延迟分析的速度和精度。

公开(公告)号：US20090055142A1

公开(公告)日：2009-02-26

申请号：US12190205

申请日：2008-08-12

申请人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma

发明人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma

IPC分类号： G06F7/60 ,  G06F17/10

CPC分类号： G06Q10/06 ,  G06Q10/04

摘要： A method for estimating a man-hours of an entire project having a series of tasks with a computer includes, inputting an estimated man-hours of the each task, acquiring model functions for extracting estimation errors included in the estimated man-hours of the each task based on an attribute of a worker who performs the each task, calculating a probability density distribution representing estimation errors depending on the attribute and a probability density distribution representing modeling errors depending on methods for estimating the man-hours for each task using the model functions, calculating man-hours of the entire project having a series of tasks for the each task using statistical methods to accumulate the probability density distribution representing estimation errors and the probability density distribution representing the modeling errors, and outputting calculating results of man-hours of the entire project to a output device.

摘要翻译： 用计算机具有一系列任务的整个项目的工时估计方法包括：输入每个任务的估计工时，获取用于提取包括在每个任务的估计工时中的估计误差的模型功能 任务基于执行每个任务的工作者的属性，根据属性计算表示估计误差的概率密度分布，以及代表建模误差的概率密度分布，这取决于使用模型函数估计每个任务的工时的方法 使用统计方法计算表示估计误差的概率密度分布和表示建模误差的概率密度分布，计算出每个任务的一系列任务的工时，并输出计算结果 整个项目到一个输出设备。

公开(公告)号：US20080244487A1

公开(公告)日：2008-10-02

申请号：US12073038

申请日：2008-02-28

申请人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma

发明人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A delay analysis support apparatus that supports analysis of delay in a target circuit includes an acquiring unit that acquires error information concerning a cell-delay estimation error that is dependent on a characterizing tool; an error calculating unit that calculates, based on the error information and a first probability density distribution concerning the cell delay of each cell and obtained from the cell delay estimated by the characterizing tool, a second probability density distribution that concerns the cell-delay estimation error of each cell; and an linking unit that links the second probability density distribution and a cell library storing therein the first probability density distribution.

摘要翻译： 支持对目标电路中的延迟进行分析的延迟分析支持装置包括获取单元，其获取与取决于特征化工具有关的信元延迟估计误差的误差信息; 误差计算单元，其基于所述误差信息和关于每个小区的小区延迟并从由所述表征工具估计的小区延迟获得的第一概率密度分布，计算涉及所述小区延迟估计误差的第二概率密度分布 的每个细胞; 以及链接单元，其将第二概率密度分布与其中存储有第一概率密度分布的单元库连接。

公开(公告)号：US20070142142A1

公开(公告)日：2007-06-21

申请号：US11589242

申请日：2006-10-30

申请人： Midori Yamaguchi ,  Yoshihisa Kodama ,  Toshiji Iida ,  Toshiyuki Shibuya ,  Tatsuya Ozone

发明人： Midori Yamaguchi ,  Yoshihisa Kodama ,  Toshiji Iida ,  Toshiyuki Shibuya ,  Tatsuya Ozone

IPC分类号： F16H59/00 ,  F16H61/00

CPC分类号： F16H61/66272 ,  F16H2061/66281

摘要： A control apparatus for an automatic transmission includes a control section having a target secondary pressure setting section configured to set a target secondary pressure within a strength limit of the belt, and an operation switching section configured to switch a shift operation from a normal speed to a high speed higher than the normal speed when a predetermined condition is satisfied. The control section is configured to control the secondary pressure regulating valve by a feedback control based on the target secondary pressure and the actual secondary pressure sensed by the hydraulic pressure sensor. The target secondary pressure setting section is configured to modify the target secondary pressure by adding a predetermined quantity when a correction initiation condition is satisfied, the condition initiation including a first condition that the shift operation is performed at a high speed by switching of the operation switching section.

摘要翻译： 一种用于自动变速器的控制装置，包括：控制部，其具有将目标二次压力设定在带的强度极限内的目标二次压力设定部;以及操作切换部，被配置为将换档动作从正常速度切换到 当满足预定条件时，高于正常速度的高速度。 控制部构成为通过基于目标二次压力和由液压传感器感测到的实际次级压力的反馈控制来控制二次压力调节阀。 目标二次压力设定部被配置为在满足校正开始条件时增加预定量来修正目标二次压力，该条件启动包括通过切换操作切换而进行高速移动操作的第一条件 部分。

公开(公告)号：US20050108669A1

公开(公告)日：2005-05-19

申请号：US11019365

申请日：2004-12-23

申请人： Toshiyuki Shibuya

发明人： Toshiyuki Shibuya

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068

摘要： A layout method in a layout apparatus for layout of an integrated circuit includes placing a plurality of cells at approximate positions according to the circuit data and placing the plurality of cells at specific positions according to the result of the placement of the plurality of cells at the approximate positions. In the placing the plurality of cells at specific positions, the plurality of cells are placed at specific positions, critical area values between cells adjacent to one another are calculated, and the specific positions of the cells are modified so as to reduce the critical area values obtained.

摘要翻译： 布线方法在集成电路布局中的布置方法包括：根据电路数据将多个单元放置在近似位置，并根据多个单元的放置结果将多个单元放置在特定位置 近似位置 在将多个单元放置在特定位置时，多个单元被放置在特定位置，计算彼此相邻的单元之间的临界区域值，并修改单元的特定位置以便减小临界面积值 获得。

公开(公告)号：US06584603B1

公开(公告)日：2003-06-24

申请号：US09667218

申请日：2000-09-21

申请人： Toshiyuki Shibuya

发明人： Toshiyuki Shibuya

IPC分类号： G06F945

CPC分类号： G06F17/5068

摘要： When a location descriptive sentence is operated, a floor plan is generated is such a way that a circuit block of fixed shape can be laid out by assigning a rotation code to the circuit block of fixed shape or merging the circuit block of fixed shape with another circuit block.

摘要翻译： 当操作位置描述语句时，产生平面布置是这样一种方式，可以通过将固定形状的电路块分配一个旋转代码或将固定形状的电路块与另一个电路块合并来固定形状的电路块 电路块。