公开(公告)号：US20110125480A1

公开(公告)日：2011-05-26

申请号：US12913425

申请日：2010-10-27

申请人： Katsumi HOMMA

发明人： Katsumi HOMMA

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： A non-transitory, computer-readable recording medium stores therein a program causing a computer to execute calculating, using respective standard deviations of first delay distributions of delay variation independent to each element included in a path among parallel paths in a circuit, standard deviation of a first delay distribution of the path when modeled as a series circuit; correcting the standard deviation of the first delay distribution for each element, using the calculated standard deviation of the first delay distribution of the path and a standard deviation of a first delay distribution of the path obtained by a statistical delay analysis on the circuit; obtaining a correlation distribution representing a correlation between delay and leak current of the circuit by executing, using the corrected standard deviation of the first delay distribution for each element, correlation analysis between delay and leak current of the target circuit; and outputting the obtained correlation distribution.

摘要翻译： 一种非暂时的计算机可读记录介质，其中存储使计算机执行计算的程序，使用与电路中的并行路径中包括的路径中的每个元素独立的延迟变化的第一延迟分布的标准偏差的标准偏差， 当建模为串联电路时路径的第一延迟分布; 使用计算出的路径的第一延迟分布的标准偏差和通过电路上的统计延迟分析获得的路径的第一延迟分布的标准偏差来校正每个元件的第一延迟分布的标准偏差; 通过使用对每个元件的第一延迟分布的校正标准偏差，通过执行目标电路的延迟和泄漏电流之间的相关分析来获得表示电路的延迟和漏电流之间的相关性的相关分布; 并输出所获得的相关分布。

公开(公告)号：US20100131249A1

公开(公告)日：2010-05-27

申请号：US12561490

申请日：2009-09-17

申请人： Katsumi HOMMA

发明人： Katsumi HOMMA

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/5036

摘要： A leakage current distribution verification support method includes a process including obtaining the estimated number L of cells in the custom macro circuit and the first arithmetic expression including a polynomial with a term having a common parameter α representing variations arising from each cell in the custom macro circuit and with a term having a parameter β representing variations arising from the entirety of the custom macro circuit, generating a second arithmetic expression including a polynomial with a term having a parameter αn (n=1, 2, . . . , L) and a term having the parameter β, setting coefficients in the polynomial included in the second arithmetic expression in such a manner that a result of calculation of the second arithmetic expression becomes equal to a result of calculation of the first arithmetic expression, and outputting the second arithmetic expression in which the coefficients have been set.

摘要翻译： 泄漏电流分布验证支持方法包括获得定制宏电路中的单元的估计数L的处理，以及第一算术表达式，其包括具有公共参数α的项的多项式，所述公共参数α表示定制宏电路中每个单元产生的变化 并且具有参数＆bgr的术语; 代表由整个定制宏电路产生的变化，产生包括具有参数αn（n = 1,2，...，L）的术语和具有参数“bgr”的项的多项式的第二算术表达式;设置 包含在第二算术表达式中的多项式的系数使得第二算术表达式的计算结果等于第一算术表达式的计算结果，并输出其中已经设置了系数的第二算术表达式 。

公开(公告)号：US07681161B2

公开(公告)日：2010-03-16

申请号：US11902489

申请日：2007-09-21

申请人： Katsumi Homma ,  Hidetoshi Matsuoka ,  Izumi Nitta ,  Toshiyuki Shibuya

发明人： Katsumi Homma ,  Hidetoshi Matsuoka ,  Izumi Nitta ,  Toshiyuki Shibuya

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.

摘要翻译： 对具有多个并行部分电路（路径）的电路进行延迟分析涉及使用基于路径中的所有电路元件的性能的指示延迟的全元延迟分布递归地积分电路的两个路径，以及指示延迟的相关延迟分布 基于路径中的电路元件之间的相关性。 使用要集成的两个路径的全元素延迟分布，针对集成路径计算全元素延迟分布。 要整合的两个路径的全元素延迟分布和相关延迟分布用于计算集成路径的总延迟分布。 总延迟分布与集成路径的全元素延迟分布一起使用，以计算集成路径的相关延迟分布。 通过递归计算，估计电路的延迟分布。

公开(公告)号：US07653889B2

公开(公告)日：2010-01-26

申请号：US11524342

申请日：2006-09-20

申请人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma ,  Hidetoshi Matsuoka

发明人： Izumi Nitta ,  Toshiyuki Shibuya ,  Katsumi Homma ,  Hidetoshi Matsuoka

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.

摘要翻译： 一种装置包括：检测单元，基于目标电路的延迟分析结果，从目标电路中的多个路径中检测目标路径，其中延迟分析的结果包括第一电路部件的延迟数据 的目标路径; 提取单元，其提取具有与所述第一电路部件相同类型的第二电路部件的延迟数据; 以及生成单元，其生成用于用第二电路部件替换第一电路部件的指令。

公开(公告)号：US20080195941A1

公开(公告)日：2008-08-14

申请号：US12002504

申请日：2007-12-17

申请人： Toshiyuki SHIBUYA ,  Katsumi HOMMA ,  Izumi NITTA

发明人： Toshiyuki SHIBUYA ,  Katsumi HOMMA ,  Izumi NITTA

IPC分类号： G06F3/00

CPC分类号： G06F17/5031

摘要： Fluctuations of cumulative delay value and delay dispersion in a path of a circuit are displayed graphically. Cumulative delay values of circuit elements in the path are obtained from delay analysis results of the circuit and dispersion is obtained from a probability density distribution of the delay of the circuit elements. Corresponding to the location of the circuit element in the path, the former and the latter are plotted on a coordinate plane.

摘要翻译： 以图形方式显示电路路径中的累积延迟值和延迟色散的波动。 从电路的延迟分析结果获得路径中的电路元件的累积延迟值，并且从电路元件的延迟的概率密度分布获得色散。 对应于电路元件在路径中的位置，前者和后者绘制在坐标平面上。

公开(公告)号：US20070204248A1

公开(公告)日：2007-08-30

申请号：US11521138

申请日：2006-09-14

申请人： Katsumi Homma ,  Toshiyuki Shibuya ,  Hidetoshi Matsuoka ,  Izumi Nitta

发明人： Katsumi Homma ,  Toshiyuki Shibuya ,  Hidetoshi Matsuoka ,  Izumi Nitta

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.

摘要翻译： 延迟分析装置接收目标电路的定时分析结果，并根据检测单元的定时分析结果从目标电路中的路径检测关键路径。 第一计算单元基于每个关键路径的平均延迟值来计算除了关键路径之外的路径的平均延迟分布。 第二计算单元计算关键路径的概率密度分布，第三计算单元基于平均延迟分布来计算所有路径的概率密度分布。 第四计算单元基于关键路径的概率密度分布和所有路径的概率密度分布来计算关键路径的统计延迟值与所有路径的统计延迟值之间的差异。

公开(公告)号：US20070074138A1

公开(公告)日：2007-03-29

申请号：US11315173

申请日：2005-12-23

申请人： Katsumi Homma ,  Toshiyuki Shibuya ,  Hidetoshi Matsuoka ,  Izumi Nitta

发明人： Katsumi Homma ,  Toshiyuki Shibuya ,  Hidetoshi Matsuoka ,  Izumi Nitta

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F2217/84

摘要： A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.

摘要翻译： 延迟分析装置包括：接收单元，其接收要分析的目标电路的定时分析的结果;检测单元，其检测具有在预定范围内的延迟的关键路径;计算统计延迟的统计延迟计算单元， 基于关键路径的延迟的累积概率分布的目标电路，以及计算结果中具有最大延迟的关键路径的延迟的概率密度分布的概率密度分布计算单元。 检测单元检测在计算的概率密度分布内具有累积延迟的x个关键路径。

公开(公告)号：US08380480B2

公开(公告)日：2013-02-19

申请号：US12913425

申请日：2010-10-27

申请人： Katsumi Homma

发明人： Katsumi Homma

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： A non-transitory, computer-readable recording medium stores therein a program causing a computer to execute calculating, using respective standard deviations of first delay distributions of delay variation independent to each element included in a path among parallel paths in a circuit, standard deviation of a first delay distribution of the path when modeled as a series circuit; correcting the standard deviation of the first delay distribution for each element, using the calculated standard deviation of the first delay distribution of the path and a standard deviation of a first delay distribution of the path obtained by a statistical delay analysis on the circuit; obtaining a correlation distribution representing a correlation between delay and leak current of the circuit by executing, using the corrected standard deviation of the first delay distribution for each element, correlation analysis between delay and leak current of the target circuit; and outputting the obtained correlation distribution.

摘要翻译： 一种非暂时的计算机可读记录介质，其中存储使计算机执行计算的程序，使用与电路中的并行路径中包括的路径中的每个元素独立的延迟变化的第一延迟分布的标准偏差的标准偏差， 当建模为串联电路时路径的第一延迟分布; 使用计算出的路径的第一延迟分布的标准偏差和通过电路上的统计延迟分析获得的路径的第一延迟分布的标准偏差来校正每个元件的第一延迟分布的标准偏差; 通过使用对每个元件的第一延迟分布的校正标准偏差，通过执行目标电路的延迟和泄漏电流之间的相关分析来获得表示电路的延迟和漏电流之间的相关性的相关分布; 并输出所获得的相关分布。

公开(公告)号：US08340946B2

公开(公告)日：2012-12-25

申请号：US12763508

申请日：2010-04-20

申请人： Katsumi Homma

发明人： Katsumi Homma

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A computer-readable recording medium stores therein a program causing a computer that accesses a simulator to execute receiving a measured yield distribution that expresses an actually measured yield distribution concerning leak current of a circuit-under-design, and model data for leak current of a cell of the circuit-under-design; providing the simulator with the model data and values for a normal distribution concerning variation components of the leak current of the cell; acquiring the leak current of the circuit-under-design; calculating, based on the acquired leak current, an estimated yield distribution concerning the leak current of the circuit-under-design; calculating values for the normal distribution that minimize error between the measured yield distribution and the estimated yield distribution; setting an initial value to the normal distribution and the calculated values for the normal distribution to the normal distribution; and outputting the estimated yield distribution that is based on the leak current of the circuit-under-design.

摘要翻译： 计算机可读记录介质存储程序，使计算机访问模拟器以执行接收测量的收益率分布，该收益分布表示关于设计中的电路的漏电流的实际测量的收益率分布，以及用于泄漏电流的模型数据 电路设计下的电池; 向模拟器提供模型数据和关于小区泄漏电流的变化分量的正态分布的值; 获取设计电路的漏电流; 基于所获得的泄漏电流计算关于设计电路的漏电流的估计产量分布; 计算正态分布的值，使得测量的产量分布与估计的收益率分布之间的误差最小化; 将正态分布的初始值设置为正态分布的正态分布的计算值; 并输出基于设计电路的漏电流的估计的收益率分布。

公开(公告)号：US08074186B2

公开(公告)日：2011-12-06

申请号：US12203636

申请日：2008-09-03

申请人： Katsumi Homma

发明人： Katsumi Homma

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A leakage current analyzing apparatus receives input of data used for analysis and indicating intra/inter-chip variation concerning the gate length of transistors constituting cells in a circuit to be designed, where the inter-chip variation is handled as a discrete probability density distribution R. Using the data input, the leakage current analyzing apparatus obtains a cumulative probability density for a leakage current value (of the circuit) that is equal to or less than each arbitrary leakage current value I1 to IJ. As a result, the leak rate of the circuit to be designed can be correctly obtained without limiting the shape of distribution.

摘要翻译： 泄漏电流分析装置接收用于分析的数据的输入，并且指示在要设计的电路中构成单元的晶体管的栅极长度的片内/片间变化，其中芯片间变化被处理为离散概率密度分布R 利用数据输入，泄漏电流分析装置获得等于或小于每个任意泄漏电流值I1至IJ的电流值（该电路的泄漏电流值）的累积概率密度。 结果，可以正确地获得要设计的电路的泄漏率，而不限制分布的形状。