发明申请
- 专利标题: CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY
- 专利标题(中): 具有降低干扰信号灵敏度的芯片载体
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申请号: US11618172申请日: 2006-12-29
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公开(公告)号: US20070210417A1公开(公告)日: 2007-09-13
- 发明人: Florian Binder , Thomas Haneder , Judith Lehmann , Manfred Schneegans , Grit Sommer
- 申请人: Florian Binder , Thomas Haneder , Judith Lehmann , Manfred Schneegans , Grit Sommer
- 申请人地址: DE Munich
- 专利权人: Qimonda AG
- 当前专利权人: Qimonda AG
- 当前专利权人地址: DE Munich
- 优先权: DE102005062932.6 20051229
- 主分类号: H01L29/00
- IPC分类号: H01L29/00
摘要:
Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.
公开/授权文献
- US07911026B2 Chip carrier with reduced interference signal sensitivity 公开/授权日:2011-03-22