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    Chip carrier substrate and production method therefor
    1.
    发明申请
    Chip carrier substrate and production method therefor 审中-公开
    芯片载体基板及其制造方法

    公开(公告)号：US20080308303A1

    公开(公告)日：2008-12-18

    申请号：US11486671

    申请日：2006-07-14

    申请人： Volker Lehmann ,  Florian Binder ,  Thomas Haneder ,  Alfred Martin ,  Judith Lehmann

    发明人： Volker Lehmann ,  Florian Binder ,  Thomas Haneder ,  Alfred Martin ,  Judith Lehmann

    IPC分类号： H05K1/03 ,  H05K3/10

    CPC分类号： H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

    摘要： Method for producing a macroporous silicon substrate suitable as a carrier for microelectronic components. Blind holes are produced from a front surface of the substrate. An insulator layer is produced on the front and rear surfaces of the substrate. Selective isotropic etching is performed from the rear surface with uncovering of blind hole ends produced such that respective blind hole walls formed by the insulator layer project from the substrate on the rear surface and are defined in this region only by the insulator layer forming the respective blind hole wall. A further insulator layer is then produced on the surfaces of the substrate. A plurality of the blind holes are then filled with a metal or a metal alloy by introducing the substrate into a melt thereof under pressure in a process chamber containing the melt. The melt is then asymmetrically cooled in the blind holes from the front surface, so that the metal or the alloy contracts toward and lies on a plane with the rear surface of the substrate. Any of the remaining unfilled blind hole ends that project from the substrate are removed.

    摘要翻译： 适用于微电子元件载体的大孔硅衬底的制造方法。 从基板的前表面产生盲孔。 在基板的前表面和后表面上产生绝缘体层。 从后表面进行选择性各向同性蚀刻，盲孔的露出被制成，使得由绝缘体层形成的各个盲孔壁从后表面上的基板突出，并且仅在形成该盲区的绝缘体层的该区域中限定 孔壁。 然后在衬底的表面上产生另外的绝缘体层。 然后通过在包含熔体的处理室中将基材在压力下引入其熔体中，用金属或金属合金填充多个盲孔。 然后熔融物在盲孔中从前表面不对称地冷却，使得金属或合金收缩并且位于与基底的后表面的平面上。 从衬底突出的任何剩余的未填充的盲孔端部被移除。

    CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY
    5.
    发明申请
    CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号：US20070210417A1

    公开(公告)日：2007-09-13

    申请号：US11618172

    申请日：2006-12-29

    申请人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    发明人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    IPC分类号： H01L29/00

    CPC分类号： H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/4602 ,  H01L2224/05599

    摘要： Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译： 载体包括具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道，其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上并具有形成在其中的第一前侧金属化层的前侧布线层，使得其包括用于将微电子器件和/或电路电连接到信号的第一极的第一电容器电极 或电源电压。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域，该区域至少部分地形成第二电容器电极，用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。

    Chip carrier with reduced interference signal sensitivity
    6.
    发明授权
    Chip carrier with reduced interference signal sensitivity 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号：US07911026B2

    公开(公告)日：2011-03-22

    申请号：US11618172

    申请日：2006-12-29

    申请人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    发明人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    IPC分类号： H01L21/02

    CPC分类号： H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/4602 ,  H01L2224/05599

    摘要： Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译： 载体包括：具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道，其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上的前侧布线层， 具有形成在其中的第一前侧金属化层，使得其包括用于将微电子器件和/或电路电连接到信号或电源电压的第一极的第一电容器电极。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域，该区域至少部分地形成第二电容器电极，用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。