发明申请
US20070226407A1 Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips 有权
用于缓冲的集成电路和方法来优化芯片中网络中的突发长度

Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips
摘要:
An integrated circuit comprising a plurality of processing modules (M, S) coupled by an interconnect means (N) is provided. A first processing module (M) communicates with a second processing module (S) based on transactions. A first wrapper means (WM1) associated to said second processing module (S) buffers data from said second processing module (S) to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module (M).
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