发明申请
US20070226407A1 Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips
有权
用于缓冲的集成电路和方法来优化芯片中网络中的突发长度
- 专利标题: Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips
- 专利标题(中): 用于缓冲的集成电路和方法来优化芯片中网络中的突发长度
-
申请号: US11569083申请日: 2005-05-13
-
公开(公告)号: US20070226407A1公开(公告)日: 2007-09-27
- 发明人: Andrei Radulescu , Kees Gerard Goossens
- 申请人: Andrei Radulescu , Kees Gerard Goossens
- 申请人地址: NL Eindhoven 5621 BA
- 专利权人: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
- 当前专利权人: KONINKLIJKE PHILIPS ELECTRONICS, N.V.
- 当前专利权人地址: NL Eindhoven 5621 BA
- 优先权: EP04102189.0 20040518
- 国际申请: PCT/IB05/51580 WO 20050513
- 主分类号: G06F13/42
- IPC分类号: G06F13/42
摘要:
An integrated circuit comprising a plurality of processing modules (M, S) coupled by an interconnect means (N) is provided. A first processing module (M) communicates with a second processing module (S) based on transactions. A first wrapper means (WM1) associated to said second processing module (S) buffers data from said second processing module (S) to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module (M).
公开/授权文献
信息查询