Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips
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    发明申请
    Integrated Circuit And Method For Buffering To Optimize Burst Length In Networks On Chips 有权
    用于缓冲的集成电路和方法来优化芯片中网络中的突发长度

    公开(公告)号:US20070226407A1

    公开(公告)日:2007-09-27

    申请号:US11569083

    申请日:2005-05-13

    IPC分类号: G06F13/42

    CPC分类号: G06F13/4208

    摘要: An integrated circuit comprising a plurality of processing modules (M, S) coupled by an interconnect means (N) is provided. A first processing module (M) communicates with a second processing module (S) based on transactions. A first wrapper means (WM1) associated to said second processing module (S) buffers data from said second processing module (S) to be transferred over said interconnect means until a first amount of data is buffered and then transfers said first amount of buffered data to said first processing module (M).

    摘要翻译: 提供了包括通过互连装置(N)耦合的多个处理模块(M,S)的集成电路。 第一处理模块(M)基于事务与第二处理模块(S)进行通信。 与所述第二处理模块(S)相关联的第一包装装置(WM1)缓冲来自所述第二处理模块(S)的数据,以便通过所述互连装置传送,直到第一数据量被缓冲,然后传送所述第一数量缓冲 数据传送到所述第一处理模块(M)。