Invention Application
- Patent Title: Interleaver and De-Interleaver
- Patent Title (中): 交织器和去交织器
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Application No.: US10592882Application Date: 2004-04-09
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Publication No.: US20070266274A1Publication Date: 2007-11-15
- Inventor: Xiaotong Lin
- Applicant: Xiaotong Lin
- Applicant Address: US PA Allentown 18109
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown 18109
- International Application: PCT/US04/11097 WO 20040409
- Main IPC: H03M13/27
- IPC: H03M13/27

Abstract:
An interleaver employs a generalized method of generating a mapping. The mapping is generated for interleaving bits of a data block and associated error detection/correction information. The data block is of length N, and the length of the error detection/correction information is P. An (N+P)×(N+P) square matrix is formed and divided into sub-blocks, where one portion of the matrix is associated with error detection/correction information and another portion is associated with data of the data block. New positions in the matrix are generated in a time sequence on a sub-block by sub-block basis based on a generator seed pair and an original position seed pair. The time sequence also corresponds to positions in an output interleaved block. Once the new position sequence is generated, the matrix is populated with data and error detection/correction information based on the corresponding time sequence. A de-interleaver performs the inverse mapping of the interleaver.
Public/Granted literature
- US07640462B2 Interleaver and de-interleaver Public/Granted day:2009-12-29
Information query
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