公开(公告)号：US20080301522A1

公开(公告)日：2008-12-04

申请号：US12189392

申请日：2008-08-11

申请人： Xiaotong Lin ,  Fan Zhou

发明人： Xiaotong Lin ,  Fan Zhou

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/2792 ,  H03M13/2703 ,  H03M13/276 ,  H03M13/2903 ,  H03M13/2909 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071

摘要： A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

摘要翻译： 结构化交织/解交织方案使得能够有效地实现基于二维产品代码（2D PC）的编码/解码。 编码器具有集成架构，其以集成的方式执行结构化交织和PC编码，其中交错数据流中的位置与基于闭合形式表达式的2D PC编码的行和列索引相关。 在一个实施例中，相应的解码器基于交织数据流中的位置与LDPC解码的行和列索引之间的相同关系实现两阶段低密度奇偶校验（LDPC）解码。

公开(公告)号：US08565270B2

公开(公告)日：2013-10-22

申请号：US13156228

申请日：2011-06-08

申请人： Peiqing Wang ,  Xiaotong Lin ,  Mehmet Tazebay ,  Linghsiao Wang

发明人： Peiqing Wang ,  Xiaotong Lin ,  Mehmet Tazebay ,  Linghsiao Wang

IPC分类号： H04J3/06

CPC分类号： H04L12/4625 ,  H04J3/0641 ,  H04J3/0644 ,  H04J3/0658 ,  H04J3/0688

摘要： A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link.

摘要翻译： 第一PHY可以经由网络链路耦合到第二PHY。 第一PHY可以从网络链路的定时主机的角色转变为网络链路的定时从站的角色。 在转换之后的第一时间间隔期间，PHY可以在第一PHY同步到第二PHY的发送时钟的同时通过链路进行半双工。 在第二时间间隔期间，PHY可以全双工通信，而第二以太网PHY与第一PHY的发送时钟同步。 同样在第二时间间隔期间，第一PHY可以确定第一PHY和第二PHY是同步的。 在确定之后，PHY可以开始网络链路上的数据的全双工通信。

公开(公告)号：US20110305165A1

公开(公告)日：2011-12-15

申请号：US13072619

申请日：2011-03-25

申请人： Peiqing Wang ,  Xiaotong Lin ,  Mehmet Tazebay

发明人： Peiqing Wang ,  Xiaotong Lin ,  Mehmet Tazebay

IPC分类号： H04L12/28

CPC分类号： H04L12/4625 ,  H04J3/0641 ,  H04J3/0644 ,  H04J3/0658 ,  H04J3/0688

摘要： Aspects of a method and system for physical-layer handshaking for timing role transition are provided. Prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more PCS code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device. The IDLE symbol(s) may be generated utilizing a second set of one or more PCS code-groups. The first set of PCS code-group(s) may be mutually exclusive with the second set of PCS code-group(s). In response to detecting a received Ethernet physical layer symbol corresponding to the second set of PCS code-groups, the second Ethernet device may make a determination to change its timing role.

摘要翻译： 提供了一种用于定时角色转换的物理层握手方法和系统。 在改变第一以太网设备的定时角色之前，第一以太网设备可以利用第一组一个或多个PCS码组通过以太网链路通信到第二以太网PHY。 响应于改变第一以太网设备的定时角色的决定，第一以太网设备可以通过以太网链路将一个或多个IDLE符号传送到第二以太网设备。 可以利用一个或多个PCS代码组的第二组来生成IDLE符号。 第一组PCS代码组可以与第二组PCS代码组相互排斥。 响应于检测到与第二组PCS代码组对应的接收到的以太网物理层符号，第二以太网设备可以做出改变其定时角色的确定。

公开(公告)号：US07734993B2

公开(公告)日：2010-06-08

申请号：US12103860

申请日：2008-04-16

申请人： Victor Krachkovsky ,  Xiaotong Lin

发明人： Victor Krachkovsky ,  Xiaotong Lin

IPC分类号： G06F11/00 ,  H03M13/00

CPC分类号： G11B20/1426 ,  G11B20/10009

摘要： Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

摘要翻译： 本发明的实施例包括用于对数据进行编码的方法和装置以及用于发送和/或存储数据的系统，其中以不违反先前建立的数据约束（诸如调制编码约束）的方式对数据进行编码和预编码。 该方法包括以下步骤：使用由至少一个调制约束定义的调制码，对调制编码信息进行奇偶校验，以及编码信息之前对数据进行调制编码。 上述步骤部分地预编码信息比特，并且以不违反调制约束的方式预编码奇偶校验位，预编码信息比特，而不是奇偶校验位，或者对信息比特和奇偶校验比特进行预编码。 此外，奇偶校验编码步骤可以以不违反调制码约束的方式执行。

公开(公告)号：US20070011502A1

公开(公告)日：2007-01-11

申请号：US11167478

申请日：2005-06-27

申请人： Xiaotong Lin ,  Fan Zhou

发明人： Xiaotong Lin ,  Fan Zhou

IPC分类号： G11C29/00

CPC分类号： H03M13/2792 ,  H03M13/2703 ,  H03M13/276 ,  H03M13/2903 ,  H03M13/2909 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071

摘要： A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. A corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

摘要翻译： 结构化交织/解交织方案使得能够有效地实现基于二维产品代码（2D PC）的编码/解码。 在一个实施例中，编码器具有集成架构，其以集成的方式执行结构化交织和PC编码，其中交织数据流中的位置与基于闭合形式表达式的2D PC编码的行和列索引相关。 相应的解码器基于交织数据流中的位置与LDPC解码的行和列索引之间的相同关系实现两阶段低密度奇偶校验（LDPC）解码。

公开(公告)号：US08205147B2

公开(公告)日：2012-06-19

申请号：US12189392

申请日：2008-08-11

申请人： Xiaotong Lin ,  Fan Zhou

发明人： Xiaotong Lin ,  Fan Zhou

IPC分类号： G06F11/00

CPC分类号： H03M13/2792 ,  H03M13/2703 ,  H03M13/276 ,  H03M13/2903 ,  H03M13/2909 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071

摘要： A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

摘要翻译： 结构化交织/解交织方案使得能够有效地实现基于二维产品代码（2D PC）的编码/解码。 编码器具有集成架构，其以集成的方式执行结构化交织和PC编码，其中交错数据流中的位置与基于闭合形式表达式的2D PC编码的行和列索引相关。 在一个实施例中，相应的解码器基于交织数据流中的位置与LDPC解码的行和列索引之间的相同关系实现两阶段低密度奇偶校验（LDPC）解码。

公开(公告)号：US07936777B2

公开(公告)日：2011-05-03

申请号：US12488232

申请日：2009-06-19

申请人： Peiqing Wang ,  Xiaotong Lin

发明人： Peiqing Wang ,  Xiaotong Lin

IPC分类号： H04L12/66

CPC分类号： H04L43/00 ,  H04L12/12 ,  Y02D50/40 ,  Y02D50/42

摘要： Embodiments of the present invention enable robust and quick parallel detection of the remote LPI request signal (rem_lpi_req) and SEND ZERO mode (SEND_Z) defined in the Energy Efficient Ethernet (EEE) standard. Embodiments do not rely on energy detection for detecting SEND_Z. Therefore, SEND_Z can be detected reliably and with minimal latency. In addition, since SEND_Z and rem_lpi_req are detected in parallel, embodiments are not concerned with the false detection of rem_lpi_req (before SEND_Z is detected) or the need to disable detection of rem_lpi_req (after SEND_Z is detected).

摘要翻译： 本发明的实施例能够实现在能效以太网（EEE）标准中定义的远程LPI请求信号（rem_lpi_req）和SEND ZERO模式（SEND_Z）的鲁棒且快速的并行检测。 实施例不依赖于检测SEND_Z的能量检测。 因此，可以可靠地检测SEND_Z并以最小的延迟。 另外，由于并行地检测到SEND_Z和rem_lpi_req，实施例不涉及rem_lpi_req的错误检测（在检测到SEND_Z之前）或者需要禁止检测rem_lpi_req（在检测到SEND_Z之后）。

公开(公告)号：US20080192378A1

公开(公告)日：2008-08-14

申请号：US12023300

申请日：2008-01-31

申请人： William Gene Bliss ,  Xiaotong Lin

发明人： William Gene Bliss ,  Xiaotong Lin

IPC分类号： G11B15/18

CPC分类号： G11B20/24 ,  G11B20/10296 ,  G11B2220/2516

摘要： A data-dependent noise predictive (DDNP) adaptation module operable to support Viterbi branch metric calculations within a hard disk drive (HDD) controller is provided. This DDNP adaptation module includes a DDNP filter tap coefficient adaptation module, a DDNP filter gain scaling module, and a DDNP bias compensation module. The combination of the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module is operable to receive an error signal and a NRZ pattern and produce tap coefficients. A whitened error signal calculation module coupled to the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module, the whitened error signal calculation module operable to calculate a whitened error signal based on the error signal, NRZ pattern, and tap coefficients. This whitened error signal is used to support the Viterbi branch metric calculations.

摘要翻译： 提供了可操作以支持硬盘驱动器（HDD）控制器内的维特比分支度量计算的数据相关噪声预测（DDNP）适配模块。 该DDNP适配模块包括一个DDNP滤波器抽头系数适配模块，一个DDNP滤波器增益调节模块和一个DDNP偏置补偿模块。 DDNP滤波器抽头系数适配模块，DDNP滤波器增益缩放模块和DDNP偏置补偿模块的组合可用于接收误差信号和NRZ模式并产生抽头系数。 一个白化的误差信号计算模块耦合到DDNP滤波器抽头系数适配模块，DDNP滤波器增益缩放模块和DDNP偏置补偿模块，白化误差信号计算模块可用于根据误差信号NRZ计算白化误差信号 图案和抽头系数。 该白化误差信号用于支持维特比分支度量计算。

公开(公告)号：US20070266274A1

公开(公告)日：2007-11-15

申请号：US10592882

申请日：2004-04-09

申请人： Xiaotong Lin

发明人： Xiaotong Lin

IPC分类号： H03M13/27

CPC分类号： H03M13/2764 ,  H03M13/2703 ,  H03M13/2721 ,  H03M13/2757 ,  H03M13/276 ,  H03M13/2778 ,  H03M13/29 ,  H03M13/2909 ,  H03M13/2918

摘要： An interleaver employs a generalized method of generating a mapping. The mapping is generated for interleaving bits of a data block and associated error detection/correction information. The data block is of length N, and the length of the error detection/correction information is P. An (N+P)×(N+P) square matrix is formed and divided into sub-blocks, where one portion of the matrix is associated with error detection/correction information and another portion is associated with data of the data block. New positions in the matrix are generated in a time sequence on a sub-block by sub-block basis based on a generator seed pair and an original position seed pair. The time sequence also corresponds to positions in an output interleaved block. Once the new position sequence is generated, the matrix is populated with data and error detection/correction information based on the corresponding time sequence. A de-interleaver performs the inverse mapping of the interleaver.

摘要翻译： 交织器采用生成映射的通用方法。 产生用于交织数据块的比特和相关联的错误检测/校正信息的映射。 数据块的长度为N，错误检测/校正信息的长度为P，形成（N + P）×（N + P）个正方形矩阵，并将其划分为子块，其中矩阵的一部分 与错误检测/校正信息相关联，另一部分与数据块的数据相关联。 基于发生器种子对和原始位置种子对，以子块为基础，以子块的时间序列生成矩阵中的新位置。 时间序列也对应于输出交错块中的位置。 一旦产生了新的位置序列，基于相应的时间序列，将矩阵填充数据和错误检测/校正信息。 解交织器执行交织器的逆映射。

公开(公告)号：US09215092B2

公开(公告)日：2015-12-15

申请号：US13158277

申请日：2011-06-10

申请人： Xiaotong Lin ,  Mehmet Tazebay ,  Peiqing Wang

发明人： Xiaotong Lin ,  Mehmet Tazebay ,  Peiqing Wang

IPC分类号： H04L12/46 ,  H04J3/06

CPC分类号： H04L12/4625 ,  H04J3/0641 ,  H04J3/0644 ,  H04J3/0658 ,  H04J3/0688

摘要： An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value.

摘要翻译： 以太网PHY可以从本地定时源接收到本地时钟适合于传播到链路伙伴的指示。 作为响应，可以启动以太网PHY中的定时器。 在以太网PHY在启动定时器之后的时间段内并且在定时器达到预定值之前的时间段中接收到链路伙伴正在传播适合于以太网PHY以同步的时钟的指示，以太网PHY 可以配置为定时从机。 在以太网PHY不接收的情况下，在启动定时器之后的时间段内，并且在定时器达到预定值之前的时间段中，指示链路伙伴正在传播适合以太网PHY同步的时钟，以太网 在定时器达到预定值时，PHY可被配置为定时主机。