发明申请
- 专利标题： METHODS FOR FORMING AN INTEGRATED CIRCUIT, INCLUDING OPENINGS IN A MOLD LAYER
- 专利标题（中）： 形成集成电路的方法，包括模具层中的开口
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申请号： US11687426申请日： 2007-03-16
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公开(公告)号： US20070286945A1公开(公告)日： 2007-12-13
- 发明人: Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
- 申请人： Peter Lahnor , Odo Wunnicke , Johannes Heitmann , Peter Moll , Andreas Orth
- 申请人地址： DE Muenchen
- 专利权人： QIMONDA AG
- 当前专利权人： QIMONDA AG
- 当前专利权人地址： DE Muenchen
- 优先权： DE102006013245.9 20060322
- 主分类号： B05D5/12
- IPC分类号： B05D5/12 ; B05D5/00
摘要：
A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.