A mixed nonvolatile memory array. In the mixed nonvolatile memory array, each nonvolatile memory cell has at least one depletion mode memory cell. The depletion mode region is composed of a gate structure and a doped region. Since the thickness of the doped region is relatively thin, a voltage is applied on the gate structure to invert the conductive type of the doped region under the gate structure. Meanwhile, a bias is applied at both terminals of the doped region so as to control the operation of the depletion mode memory cell. In addition, each nonvolatile memory cell of the mixed nonvolatile memory array further comprises an enhanced mode memory cell. Therefore, each nonvolatile memory cell provides at least four carrier storage spaces so that the numbers of bits storing in a unit memory device is increased.