Invention Application
- Patent Title: METHOD OF FABRICATING SEMICONDUCTOR INTERCONNECTIONS
- Patent Title (中): 制造半导体互连的方法
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Application No.: US11765006Application Date: 2007-06-19
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Publication No.: US20080014743A1Publication Date: 2008-01-17
- Inventor: Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
- Applicant: Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
- Applicant Address: JP Kobe-shi
- Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
- Current Assignee: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
- Current Assignee Address: JP Kobe-shi
- Priority: JP2006-192153 20060712
- Main IPC: H01L21/768
- IPC: H01L21/768

Abstract:
A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
Public/Granted literature
- US07781339B2 Method of fabricating semiconductor interconnections Public/Granted day:2010-08-24
Information query
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