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公开(公告)号：US07538027B2
公开(公告)日：2009-05-26
申请号：US11532796
申请日：2006-09-18
申请人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/4763
CPC分类号： H01L21/76882 , H01L21/76843 , H01L21/76867 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.
摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹陷中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会引起电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。
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公开(公告)号：US20080014743A1
公开(公告)日：2008-01-17
申请号：US11765006
申请日：2007-06-19
申请人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76867
摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。
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公开(公告)号：US20070218690A1
公开(公告)日：2007-09-20
申请号：US11532796
申请日：2006-09-18
申请人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Masao Mizuno , Mikako Takeda , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/44
CPC分类号： H01L21/76882 , H01L21/76843 , H01L21/76867 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.
摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹部中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会导致电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。
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公开(公告)号：US07781339B2
公开(公告)日：2010-08-24
申请号：US11765006
申请日：2007-06-19
申请人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
发明人： Takashi Onishi , Mikako Takeda , Masao Mizuno , Susumu Tsukimoto , Tatsuya Kabe , Toshifumi Morita , Miki Moriyama , Kazuhiro Ito , Masanori Murakami
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76867
摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.
摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。
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公开(公告)号：US20050029011A1
公开(公告)日：2005-02-10
申请号：US10911148
申请日：2004-08-03
CPC分类号： H01L23/3735 , H01L24/72 , H01L2224/32225 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H05K1/0271 , H05K1/0306 , H05K3/3436 , H05K3/368 , H05K3/4626 , H05K3/4629 , H05K3/4688 , H05K2201/0212 , H05K2201/068 , Y02P70/613 , H01L2924/00
摘要： A circuit board including a plurality of substrates fixed on a main substrate with solder, wherein the plurality of substrates include a substrate having a smaller thermal expansion coefficient than the main substrate, and wherein the plurality of substrates are made by bonding together a ceramic substrate and a substrate having a higher strength than the ceramic substrate, with the higher-strength substrate bonded to the main substrate side of the ceramic substrate. Since a substrate having a higher strength than a ceramic substrate is bonded to the main substrate side of the ceramic substrate, it is possible to reduce the thermal stress applied to the ceramic substrate side of the circuit board so as to prevent cracking in the ceramic substrate, thus improving the reliability of the circuit board against a thermal stress.
摘要翻译： 一种电路板，包括用焊料固定在主基板上的多个基板，其中所述多个基板包括具有比所述主基板更小的热膨胀系数的基板，并且其中所述多个基板通过将陶瓷基板和 具有比陶瓷衬底高的强度的衬底，其中较高强度衬底粘合到陶瓷衬底的主衬底侧。 由于具有比陶瓷基板更高的强度的基板被接合到陶瓷基板的主基板侧，因此可以降低施加到电路板的陶瓷基板侧的热应力，以防止陶瓷基板中的开裂 ，从而提高电路板抵抗热应力的可靠性。
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公开(公告)号：US4389548A
公开(公告)日：1983-06-21
申请号：US248330
申请日：1981-03-27
申请人： Eiji Morikawa , Toshifumi Morita , Masayuki Hirate
发明人： Eiji Morikawa , Toshifumi Morita , Masayuki Hirate
CPC分类号： H04R17/00
摘要： In an acoustic transducer comprising a piezoelectric element for driving a speaker diaphragm, there is provided a cushioning member between a frame body and the piezoelectric element wherein said cushioning member is preliminarily adhered onto the top face of a bottom portion of the frame body by means of an adhering layer formed on the bottom face of the cushioning member with the piezoelectric element preliminarily adhered on the top face of the cushioning member by means of an adhering layer formed on the top face of the cushioning member so as to facilitate to mount the piezoelectric element and a speaker diaphragm on the frame body.
摘要翻译： 在包括用于驱动扬声器振动膜的压电元件的声学换能器中，在框架体和压电元件之间设置有缓冲构件，其中所述缓冲构件通过以下方式预先粘附到框体的底部的顶面上： 通过形成在缓冲部件的顶面上的粘合层，预先将缓冲部件的底面上形成有粘合层的压电元件预先粘附在缓冲部件的顶面上，以便于安装压电元件 以及在框体上的扬声器振动膜。
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