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    Method of fabricating semiconductor interconnections
    3.
    发明授权
    Method of fabricating semiconductor interconnections 失效
    制造半导体互连的方法

    公开(公告)号：US07781339B2

    公开(公告)日：2010-08-24

    申请号：US11765006

    申请日：2007-06-19

    申请人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76867

    摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.

    摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

    Steel sheet for dissimilar materials weldbonding to aluminum material and dissimilar materials bonded body
    4.
    发明授权
    Steel sheet for dissimilar materials weldbonding to aluminum material and dissimilar materials bonded body 有权
    用于不同材料的钢板焊接到铝材料和异种材料粘结体

    公开(公告)号：US07521129B2

    公开(公告)日：2009-04-21

    申请号：US11436703

    申请日：2006-05-19

    申请人： Mikako Takeda ,  Wataru Urushihara ,  Katsushi Matsumoto ,  Jun Katoh

    发明人： Mikako Takeda ,  Wataru Urushihara ,  Katsushi Matsumoto ,  Jun Katoh

    IPC分类号： B32B15/04

    CPC分类号： C22C21/06 ,  B23K35/0261 ,  B23K35/286 ,  B32B15/012 ,  C21D9/46 ,  C22C21/02 ,  C22C21/08 ,  C22C38/02 ,  C22C38/04 ,  C22C38/12 ,  C22C38/22 ,  C22C38/26 ,  C22C38/28 ,  C22C38/34 ,  Y10T428/12472 ,  Y10T428/12757

    摘要： Disclosed is a steel sheet for dissimilar materials weldbonding to an aluminum material, the steel sheet containing, in mass, C: 0.02 to 0.3%, Si: 0.2 to 5.0%, Mn: 0.2 to 2.0%, and Al: 0.002 to 0.1%, further one or more of Ti: 0.005 to 0.10%, Nb: 0.005 to 0.10%, Cr: 0.05 to 1.0%, and Mo: 0.01 to 1.0%, and the balance consisting of Fe and unavoidable impurities. In the steel sheet, (i) the proportion of the oxide containing Mn and Si by 1 at. % or more in total in the external oxide layer which is newly formed after an original oxide layer having already existed on the surface of the steel sheet is once removed and now exists on the surface of the base steel material of the steel sheet is 50 to 80% in terms of the average proportion of the total length of the oxide to 1 μm length of the interface between the base steel material and the external oxide layer nearly in the horizontal direction, (ii) the proportion of the internal oxide, including oxide at the grain boundary, which exists in the steel region up to the depth of 10 μm from the surface of said base steel material of said steel sheet and contains Mn and Si by 1 at. % or more in total is 3% or more to less than 10% in terms of the average area percentage of said internal oxide in the visual field of 10 μm2 of said steel region, (iii) the proportion of the internal oxide, including oxide at the grain boundary, which exists in the steel region exceeding 10 μm in depth from the surface of said base steel material of said steel sheet and contains Mn and Si by 1 at. % or more in total is 0.1% or less in terms of the average area percentage of said internal oxide in the visual field of 10 μm2 of said steel region.

    摘要翻译： 公开了一种用于与铝材料焊接的不同材料的钢板，该钢板以质量计含有C：0.02〜0.3％，Si：0.2〜5.0％，Mn：0.2〜2.0％，Al：0.002〜0.1％ ，进一步Ti：0.005〜0.10％，Nb：0.005〜0.10％，Cr：0.05〜1.0％，Mo：0.01〜1.0％，余量由Fe和不可避免的杂质组成。 在钢板中，（i）含有Mn和Si的氧化物的比例为1at。 在钢板表面已经存在的原始氧化物层被一次除去之后新形成的外部氧化物层中，总共存在％以上，现在存在于钢板的基体钢材的表面上，为50〜 以基本钢材和外部氧化物层之间的界面几乎在水平方向上的氧化物总长度与1mm长度的平均比例为80％，（ii）内部氧化物（包括氧化物）的比例 在与所述钢板的所述基体钢材的表面直径相距10μm的钢区域存在的晶界，其含有Mn和Si为1at。 所述钢区域的10mum2的视野内的所述内部氧化物的平均面积百分比为3％以上〜小于10％，（iii）包含氧化物的内部氧化物的比例 在与所述钢板的所述基材的表面相比，钢区域的厚度超过10μm的晶界，并且含有Mn和Si为1at。 所述钢区域的10mum2的视野内的所述内部氧化物的平均面积百分比，总计为0.1％以下。

    METAL THIN FILM FOR INTERCONNECTION OF SEMICONDUCTOR DEVICE, INTERCONNECTION FOR SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHOD
    5.
    发明申请
    METAL THIN FILM FOR INTERCONNECTION OF SEMICONDUCTOR DEVICE, INTERCONNECTION FOR SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHOD 有权
    用于半导体器件互连的金属薄膜，用于半导体器件的互连及其制造方法

    公开(公告)号：US20070145586A1

    公开(公告)日：2007-06-28

    申请号：US11465626

    申请日：2006-08-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53233 ,  H01L21/2855 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device.More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.

    摘要翻译： 提供了用于制造半导体器件的镶嵌互连的金属薄膜，其在高压退火期间表现出优异的高温流动性，并且可以制造具有低电阻和稳定高质量的半导体器件的互连。 还提供了用于半导体器件的互连。 更具体地说，一种用作半导体器件的互连的金属薄膜，其包含含有不小于0.4原子％至不大于2.0原子％的含有N的Cu合金; 以及通过在形成在半导体衬底上并形成有凹槽的绝缘体膜上形成金属薄膜而制造的半导体器件的互连，并且通过高压退火工艺在槽内填充金属薄膜 被提供。

    Fabrication method for semiconductor interconnections
    10.
    发明授权
    Fabrication method for semiconductor interconnections 有权
    半导体互连的制造方法

    公开(公告)号：US07538027B2

    公开(公告)日：2009-05-26

    申请号：US11532796

    申请日：2006-09-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76882 ,  H01L21/76843 ,  H01L21/76867 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

    摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹陷中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会引起电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。