发明申请
- 专利标题: PLL oscillation circuit
- 专利标题(中): PLL振荡电路
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申请号: US11812520申请日: 2007-06-19
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公开(公告)号: US20080042708A1公开(公告)日: 2008-02-21
- 发明人: Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
- 申请人: Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
- 优先权: JP2006-168626 20060619
- 主分类号: H03L7/091
- IPC分类号: H03L7/091
摘要:
A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.
公开/授权文献
- US07656208B2 PLL oscillation circuit 公开/授权日:2010-02-02
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