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公开(公告)号：US07791416B2
公开(公告)日：2010-09-07
申请号：US12222530
申请日：2008-08-11
申请人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
发明人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
摘要： A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.
摘要翻译： 提供一种可以吸收由于温度和个体差异引起的相位噪声特性的变化并且具有在宽频带中稳定的相位噪声抑制特性的PLL电路。 PLL电路在后续阶段包括用于存储用于控制环路增益的第一参数的第一寄存器，用于将相位比较器的输出乘以第一参数的第一乘法器，用于存储用于控制的第二参数的第二寄存器 响应特性，用于将第一乘法器的输出乘以第二参数的第二乘法器和用于根据使用频带，环境温度和设备个体差异来设置第一和第二寄存器中的最佳参数的CPU。 通过将环路增益和响应特性控制为最佳值，实现了宽频带中良好的抑制特性。
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公开(公告)号：US07656208B2
公开(公告)日：2010-02-02
申请号：US11812520
申请日：2007-06-19
申请人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
发明人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
IPC分类号： H03L7/06
摘要： A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.
摘要翻译： 数字控制PLL振荡电路具有VCO，分频器，参考振荡电路，A / D转换器，相位比较器，数字滤波器，D / A转换器和模拟滤波器。 从参考振荡电路提供的参考信号通过窄带晶体滤波器（MCF）输出到A / D转换器，以消除参考信号中包含的噪声，抖动和寄生波，从而可以防止相位噪声 VCO输出的特性和寄生特性降低。
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公开(公告)号：US20080042708A1
公开(公告)日：2008-02-21
申请号：US11812520
申请日：2007-06-19
申请人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
发明人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
IPC分类号： H03L7/091
摘要： A digitally controlled PLL oscillation circuit has a VCO, a frequency divider, a reference oscillation circuit, an A/D converter, a phase comparator, a digital filter, a D/A converter, and an analog filter. A reference signal supplied from the reference oscillation circuit is output through a narrow-band crystal filter (MCF) to the A/D converter to cancel noise, jitter and a spurious wave included in the reference signal, making it possible to prevent the phase noise characteristic and spurious characteristic of a VCO output from being degraded.
摘要翻译： 数字控制PLL振荡电路具有VCO，分频器，参考振荡电路，A / D转换器，相位比较器，数字滤波器，D / A转换器和模拟滤波器。 从参考振荡电路提供的参考信号通过窄带晶体滤波器（MCF）输出到A / D转换器，以消除参考信号中包含的噪声，抖动和寄生波，从而可以防止相位噪声 VCO输出的特性和寄生特性降低。
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公开(公告)号：US20090021312A1
公开(公告)日：2009-01-22
申请号：US12222530
申请日：2008-08-11
申请人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
发明人： Hiroki Kimura , Tsukasa Kobata , Yasuo Kitayama , Naoki Onishi
IPC分类号： H03L7/099
摘要： It has been difficult that conventional PLL circuits have a suppression characteristic of suppressing the phase noise which is free of variation due to temperature and individual difference and stable in a wide frequency band. The present invention provides a PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.
摘要翻译： 传统的PLL电路难以抑制由于温度和个体差异而没有变化并且在宽频带中稳定的相位噪声的抑制特性。 本发明提供一种可以吸收由于温度和个体差异引起的相位噪声特性的变化的PLL电路，并且具有在宽频带中稳定的相位噪声抑制特性。 PLL电路在后续阶段包括用于存储用于控制环路增益的第一参数的第一寄存器，用于将相位比较器的输出乘以第一参数的第一乘法器，用于存储用于控制的第二参数的第二寄存器 响应特性，用于将第一乘法器的输出乘以第二参数的第二乘法器和用于根据使用频带，环境温度和设备个体差异来设置第一和第二寄存器中的最佳参数的CPU。 通过将环路增益和响应特性控制为最佳值，实现了宽频带中良好的抑制特性。
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公开(公告)号：US07893774B2
公开(公告)日：2011-02-22
申请号：US12826236
申请日：2010-06-29
申请人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
发明人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。
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公开(公告)号：US20090039973A1
公开(公告)日：2009-02-12
申请号：US12219452
申请日：2008-07-22
申请人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
发明人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
IPC分类号： H03B5/08
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。
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公开(公告)号：US20100264962A1
公开(公告)日：2010-10-21
申请号：US12826236
申请日：2010-06-29
申请人： Yasuo KITAYAMA , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
发明人： Yasuo KITAYAMA , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
IPC分类号： H03L7/08
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。
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公开(公告)号：US07821344B2
公开(公告)日：2010-10-26
申请号：US12219452
申请日：2008-07-22
申请人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
发明人： Yasuo Kitayama , Hiroki Kimura , Naoki Onishi , Nobuo Tsukamoto
摘要： A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.
摘要翻译： VCO驱动电路和频率合成器，其中从VCO控制端子观察的阻抗减小，以防止VCO相位噪声特性降级。 VCO驱动电路和具有VCO驱动电路的频率合成器，其包括具有粗略调整频率的接收数字数据的粗调DAC以输出模拟信号; 微调DAC，其接收具有微调频率的数字数据，以输出模拟信号; 低响应速度LPF5，其从粗调DAC输出信号中去除噪声，然后将所得到的信号作为输入提供给VCO控制端; 高响应速度LPF7，其将来自微调DAC的输出信号转换为电压，从而平滑信号; 将LPF5的输入级与LPF7的输入级连接的电阻; 以及用于提供电容耦合的电容器，使得LPF7的输出被添加到LPF5的输出。
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公开(公告)号：US08125255B2
公开(公告)日：2012-02-28
申请号：US12929857
申请日：2011-02-22
申请人： Hiroki Kimura , Naoki Onishi , Shoichi Tsuchiya
发明人： Hiroki Kimura , Naoki Onishi , Shoichi Tsuchiya
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , G06F1/0328
摘要： Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.
摘要翻译： 提供一种在不降低噪声特性的同时抑制功耗的同时提高可靠性的PLL电路。 PLL电路包括将VCO的输出频率Fout分频的PLL IC，将相位与参考信号进行比较，并将相位差作为控制电压反馈到VCO。 控制电路能够精细地设定DDS电路中的参考频率Fref和输出频率Fdds，DDS电路基于频率的组合，生成Fref的Fdds和其整数倍频率的折叠信号。 第一AMP放大信号，可变滤波器选择所需的Fdd（所需），第二AMP放大信号并将其作为参考信号提供给PLL IC。 控制电路还向PLL IC提供分频比N.
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公开(公告)号：US20110204935A1
公开(公告)日：2011-08-25
申请号：US12929857
申请日：2011-02-22
申请人： Hiroki Kimura , Naoki Onishi , Shoichi Tsuchiya
发明人： Hiroki Kimura , Naoki Onishi , Shoichi Tsuchiya
IPC分类号： H03L7/099
CPC分类号： H03L7/08 , G06F1/0328
摘要： Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.
摘要翻译： 提供一种在不降低噪声特性的同时抑制功耗的同时提高可靠性的PLL电路。 PLL电路包括将VCO的输出频率Fout分频的PLL IC，将相位与参考信号进行比较，并将相位差作为控制电压反馈到VCO。 控制电路能够精细地设定DDS电路中的参考频率Fref和输出频率Fdds，DDS电路基于频率的组合，生成用于Fref的Fdds和其整数倍频率的折叠信号。 第一AMP放大信号，可变滤波器选择所需的Fdd（所需），第二AMP放大信号并将其作为参考信号提供给PLL IC。 控制电路还向PLL IC提供分频比N.
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