Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods

Invention Application

US20080044981A1 Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods 审中-公开

Title translation: 沟槽隔离方法，使用沟槽隔离方法形成栅极结构的方法和使用沟槽隔离方法制造非易失性存储器件的方法

Please log in to see more content

Patent Title: Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods
Patent Title (中): 沟槽隔离方法，使用沟槽隔离方法形成栅极结构的方法和使用沟槽隔离方法制造非易失性存储器件的方法
Application No.: US11769042

Application Date: 2007-06-27
Publication No.: US20080044981A1

Publication Date: 2008-02-21
Inventor: Jung Geun Jee , Won-Jun Jang , Woong Lee , Ho-Min Son , Won-Jun Lee , Hyoeng-Ki Kim , Jung-Hyun Park
Applicant: Jung Geun Jee , Won-Jun Jang , Woong Lee , Ho-Min Son , Won-Jun Lee , Hyoeng-Ki Kim , Jung-Hyun Park
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Priority: KR10-2006-0063897 20060707
Main IPC: H01L21/3205
IPC: H01L21/3205 ; H01L21/762

Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods

Abstract:

Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask. The trench is substantially narrower than the second opening and has a sidewall that has a second inclination angle that is substantially larger than the first inclination angle.

Abstract(Chinese):

提供制造包括在半导体衬底上形成掩模图案的半导体器件的方法。掩模图案限定了至少部分地暴露半导体衬底并且在衬垫氧化物层图案上包括衬垫氧化物层和氮化物层图案的第一开口。氮化物层具有基本上大于衬垫氧化物层图案的线宽。通过至少部分去除通过第一开口暴露的半导体衬底的一部分，形成连接到第一开口的第二开口。第二开口具有具有第一倾斜角并且至少部分地暴露半导体衬底的侧壁。通过使用掩模图案蚀刻通过第二开口暴露的半导体衬底的一部分来形成连接到第二开口的沟槽作为蚀刻掩模。沟槽基本上比第二开口窄，并且具有侧壁，该侧壁的第二倾斜角度基本上大于第一倾斜角度。

Information query

Global Dossier Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3205	......非绝缘层的沉积，例如绝缘层上的导电层或电阻层；这些层的后处理（电极的制造入H01L21/28）