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24 条记录 (耗时 0.015 秒)

    Storage electrode of a capacitor and a method of forming the same
    2.
    发明授权
    Storage electrode of a capacitor and a method of forming the same 有权
    电容器的存储电极及其形成方法

    公开(公告)号：US07723182B2

    公开(公告)日：2010-05-25

    申请号：US11291798

    申请日：2005-11-30

    申请人： Won-Jun Jang ,  In-Sun Park ,  Jae-Young Park ,  Ki-Vin Im ,  Yong-Woo Hyung

    发明人： Won-Jun Jang ,  In-Sun Park ,  Jae-Young Park ,  Ki-Vin Im ,  Yong-Woo Hyung

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10852

    摘要： In an embodiment, a storage electrode of a capacitor in a semiconductor device is resistant to inadvertent etching during its manufacturing processes. A method of forming the storage electrode of the capacitor is described. The storage electrode of the capacitor may include a first metal layer electrically connected with a source region of a transistor through a contact plug penetrating an insulating layer on a semiconductor substrate. A polysilicon layer may then be formed on the first metal layer. A second metal layer is formed on the polysilicon layer.

    摘要翻译： 在一个实施例中，半导体器件中的电容器的存储电极在其制造工艺期间耐受无意的蚀刻。 描述形成电容器的存储电极的方法。 电容器的存储电极可以包括通过穿过半导体衬底上的绝缘层的接触插塞与晶体管的源极区域电连接的第一金属层。 然后可以在第一金属层上形成多晶硅层。 在多晶硅层上形成第二金属层。

    Non-volatile memory device and method of fabricating the same
    5.
    发明授权
    Non-volatile memory device and method of fabricating the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US08431983B2

    公开(公告)日：2013-04-30

    申请号：US12650367

    申请日：2009-12-30

    申请人： Woong Lee ,  Jung-Yoon Ko ,  Sang-Kyoung Lee ,  Ho-Min Son ,  Won-Jun Jang ,  Jung-Geun Jee

    发明人： Woong Lee ,  Jung-Yoon Ko ,  Sang-Kyoung Lee ,  Ho-Min Son ,  Won-Jun Jang ,  Jung-Geun Jee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/66825

    摘要： A non-volatile memory device and a method of fabricating the same are provided. The method can include disposing an isolation layer on a semiconductor substrate. The isolation layer may protrude from the main surface of the semiconductor substrate and define an active region. In a recess defined by the protrusion of the isolation layer and the active region, a diffusion-retarding poly pattern and a floating gate may be formed in sequence. A control gate may be disposed on the isolation layer to cover the diffusion-retarding poly pattern and the floating gate.

    摘要翻译： 提供了一种非易失性存储器件及其制造方法。 该方法可以包括在半导体衬底上设置隔离层。 隔离层可以从半导体衬底的主表面突出并限定有源区。 在由隔离层和有源区的突起限定的凹部中，可以依次形成扩散阻滞多晶型和浮栅。 控制栅极可以设置在隔离层上以覆盖扩散阻滞多晶型图案和浮动栅极。

    Non-volatile memory device and method of manufacturing the same
    7.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20080105915A1

    公开(公告)日：2008-05-08

    申请号：US11605317

    申请日：2006-11-29

    申请人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    发明人： Jung-Hyun Park ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7881 ,  H01L29/66825

    摘要： A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

    摘要翻译： 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层，设置在衬底的表面部分中以限定有源区的场绝缘图案，每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构，以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。

    Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods
    9.
    发明申请
    Trench Isolation Methods, Methods of Forming Gate Structures Using the Trench Isolation Methods and Methods of Fabricating Non-Volatile Memory Devices Using the Trench Isolation Methods 审中-公开
    沟槽隔离方法，使用沟槽隔离方法形成栅极结构的方法和使用沟槽隔离方法制造非易失性存储器件的方法

    公开(公告)号：US20080044981A1

    公开(公告)日：2008-02-21

    申请号：US11769042

    申请日：2007-06-27

    申请人： Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

    发明人： Jung Geun Jee ,  Won-Jun Jang ,  Woong Lee ,  Ho-Min Son ,  Won-Jun Lee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park

    IPC分类号： H01L21/3205 ,  H01L21/762

    CPC分类号： H01L21/76232

    摘要： Methods of fabricating semiconductor devices including forming a mask pattern on a semiconductor substrate are provided. The mask pattern defines a first opening that at least partially exposes the semiconductor substrate and includes a pad oxide layer and a nitride layer pattern on the pad oxide layer pattern. The nitride layer has a line width substantially larger than the pad oxide layer pattern. A second opening that is connected to the first opening is formed by at least partially removing a portion of the semiconductor substrate exposed through the first opening. The second opening has a sidewall that has a first inclination angle and at least partially exposing the semiconductor substrate. A trench connected to the second opening is formed by etching a portion of the semiconductor substrate exposed through the second opening using the mask pattern as an etch mask. The trench is substantially narrower than the second opening and has a sidewall that has a second inclination angle that is substantially larger than the first inclination angle.

    摘要翻译： 提供制造包括在半导体衬底上形成掩模图案的半导体器件的方法。 掩模图案限定了至少部分地暴露半导体衬底并且在衬垫氧化物层图案上包括衬垫氧化物层和氮化物层图案的第一开口。 氮化物层具有基本上大于衬垫氧化物层图案的线宽。 通过至少部分去除通过第一开口暴露的半导体衬底的一部分，形成连接到第一开口的第二开口。 第二开口具有具有第一倾斜角并且至少部分地暴露半导体衬底的侧壁。 通过使用掩模图案蚀刻通过第二开口暴露的半导体衬底的一部分来形成连接到第二开口的沟槽作为蚀刻掩模。 沟槽基本上比第二开口窄，并且具有侧壁，该侧壁的第二倾斜角度基本上大于第一倾斜角度。

    Method of forming a thin layer and method of manufacturing a semiconductor device
    10.
    发明申请
    Method of forming a thin layer and method of manufacturing a semiconductor device 有权
    形成薄层的方法和制造半导体器件的方法

    公开(公告)号：US20080064171A1

    公开(公告)日：2008-03-13

    申请号：US11589866

    申请日：2006-10-31

    申请人： Won-Jun Jang ,  Ho-Min Son ,  Woong Lee ,  Yong-Woo Hyung ,  Jung-Geun Jee

    发明人： Won-Jun Jang ,  Ho-Min Son ,  Woong Lee ,  Yong-Woo Hyung ,  Jung-Geun Jee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539 ,  H01L27/11568 ,  H01L29/517 ,  H01L29/518

    摘要： In a method of forming a thin layer (e.g., a charge trapping nitride layer) of a semiconductor device (e.g. a charge trapping type non-volatile memory device), the nitride layer may be formed on a first area of a substrate. A blocking layer may be formed on the nitride layer. An oxide layer may be formed on a second area of the substrate while preventing or reducing an oxidation of the nitride layer by a radical oxidation process in which oxygen radicals react with the second area of the substrate and the blocking layer in the first area of the substrate. The nitride layer may ensure sufficient charge trapping sites and may have a uniform thickness without oxidation thereof in the radical oxidation process.

    摘要翻译： 在形成半导体器件（例如电荷俘获型非易失性存储器件）的薄层（例如，电荷捕获氮化物层）的方法中，可以在衬底的第一区域上形成氮化物层。 可以在氮化物层上形成阻挡层。 可以在衬底的第二区域上形成氧化物层，同时通过自由基氧化工艺防止或减少氮化物层的氧化，其中氧自由基与衬底的第二区域反应，并且阻挡层在第一区域中 基质。 氮化物层可以确保足够的电荷俘获位点，并且可以具有均匀的厚度，而不会在自由基氧化过程中氧化。