发明申请
- 专利标题： Processor executing SIMD instructions
- 专利标题（中）： 处理器执行SIMD指令
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申请号： US11896369申请日： 2007-08-31
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公开(公告)号： US20080046688A1公开(公告)日： 2008-02-21
- 发明人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
- 申请人： Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
- 优先权： JP2002-280077 20020925
- 主分类号： G06F15/80
- IPC分类号： G06F15/80 ; G06F9/315
摘要：
A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
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