公开(公告)号：US09189989B2

公开(公告)日：2015-11-17

申请号：US13393349

申请日：2011-06-09

申请人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

发明人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

IPC分类号： G09G3/28 ,  G09G3/288 ,  G09G3/293 ,  G09G3/20 ,  G09G5/395

CPC分类号： G09G3/288 ,  G09G3/2022 ,  G09G3/293 ,  G09G5/395 ,  G09G2320/103

摘要： A plasma display system restricts peak data traffic when a shared memory is used. In the plasma display system, a control unit prohibits a moving picture decoder from accessing a shared memory while an SF reading unit is reading, from the shared memory, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit permits the moving picture decoder to access the shared memory while the SF reading unit is not reading the SF pixel data from the shared memory during a sustain discharge period.

摘要翻译： 当使用共享存储器时，等离子体显示系统限制峰值数据流量。 在等离子体显示系统中，控制单元在SF读取单元正在从共享存储器读取作为多个子场中要照明的单元的信息的SF像素数据时，禁止运动图像解码器访问共享存储器。 另一方面，控制单元允许运动图像解码器访问共享存储器，而SF读取单元在维持放电期间未从共享存储器读取SF像素数据。

公开(公告)号：US08719827B2

公开(公告)日：2014-05-06

申请号：US13179614

申请日：2011-07-11

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F1/00

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US07934082B2

公开(公告)日：2011-04-26

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F9/48

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括处理器，数据处理单元，其在从处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中，所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器向处理器发出执行异常处理程序的中断请求。

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。

公开(公告)号：US07386707B2

公开(公告)日：2008-06-10

申请号：US10338408

申请日：2003-01-08

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30 ,  G06F9/40

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US07315934B2

公开(公告)日：2008-01-01

申请号：US10377328

申请日：2003-02-28

申请人： Hiroyuki Morishita ,  Atsushi Ito ,  Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara ,  Akira Miyoshi ,  Hiroshi Kadota

发明人： Hiroyuki Morishita ,  Atsushi Ito ,  Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara ,  Akira Miyoshi ,  Hiroshi Kadota

IPC分类号： G06F15/76

CPC分类号： G06F9/3012 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3885

摘要： A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

摘要翻译： 数据处理器具有16个处理元件，每个处理元件包括寄存器文件和算术逻辑单元。 网络单元连接处理元件的寄存器文件和处理元件的算术逻辑单元。 网络单元具有选择器，用于同时执行多个数据传送，每个数据传输由一个处理元件的寄存器文件制成到另一个处理元件的操作单元。 通过提供可以执行这种同时数据传输的该选择器，即使在操作数分配等中发生改变，也可以保持处理元件的处理效率。

公开(公告)号：US07228064B2

公开(公告)日：2007-06-05

申请号：US10211716

申请日：2002-08-02

申请人： Yoshiyuki Wada ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Yukiharu Ieda

发明人： Yoshiyuki Wada ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Yukiharu Ieda

IPC分类号： H04N7/26 ,  H03N7/40

CPC分类号： H04N9/7921 ,  H04N5/78266 ,  H04N9/8042 ,  H04N9/8047 ,  H04N19/42

摘要： The present invention provides an image decoding apparatus that realizes speed-up processing of taking out an MR (macroblock remainder) from a fixed length unit that consists of a first DCT block and the MR, without increasing cost. A Setup processor 3 outputs one out of a plurality of fixed length units that constitute an SB (synchronized block). First, calculation is performed for a length from a beginning of the fixed length unit to a EOB (end of block) that is included in the fixed length unit. The calculated length is then used as an offset in taking out the MR. Then an end portion of a second DCT block that is included in the MR is combined with a corresponding beginning portion of the second DCT block, in order to obtain the complete second DCT block. The complete second DCT block is outputted to a variable length code decoder 13.

摘要翻译： 本发明提供一种图像解码装置，其实现从由第一DCT块和MR组成的固定长度单元取出MR（宏块余数）的加速处理，而不增加成本。 安装处理器3输出构成SB（同步块）的多个固定长度单元中的一个。 首先，从固定长度单位的开始到包括在固定长度单位中的EOB（块末尾）的长度进行计算。 然后将计算出的长度用作取出MR的偏移量。 然后，包括在MR中的第二DCT块的结束部分与第二DCT块的对应开始部分组合，以便获得完整的第二DCT块。 完整的第二DCT块被输出到可变长度码解码器13。

公开(公告)号：US07079583B2

公开(公告)日：2006-07-18

申请号：US10007248

申请日：2001-10-24

申请人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

发明人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

IPC分类号： H04N7/12

CPC分类号： H04N19/90 ,  H04N5/4401 ,  H04N21/426 ,  H04N21/42607 ,  H04N21/42653 ,  H04N21/42692 ,  H04N21/4302 ,  H04N21/4341

摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

公开(公告)号：US06987811B2

公开(公告)日：2006-01-17

申请号：US10048360

申请日：2001-05-31

申请人： Takaharu Tanaka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

发明人： Takaharu Tanaka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

IPC分类号： H04N7/12

CPC分类号： H03M7/40 ,  H04N19/129 ,  H04N19/132 ,  H04N19/18 ,  H04N19/42 ,  H04N19/60

摘要： The speed of decoding processing for variable-length coded image data is improved. The image processor includes a variable-length decoding unit for variable-length decoding input data and outputting a pair of the run length of zero coefficients and a non-zero coefficient; an inverse quantization unit for subjecting the non-zero coefficient to inverse quantization and obtaining inverse quantized data to be output; an address setting unit for carrying out inverse scanning, obtaining an address for storing the inverse quantized data on the basis of the run length of zero coefficients and specifying the address in the data storage unit; a write information storage unit for setting a write flag in an address thereof corresponding to the specified address; and a data reading unit for reading data from the data storage unit, and on the basis of information stored in the write information storage unit, directly outputting data from the address specified by the address setting unit while substituting a predetermined value for data from an address other than the specified address to output the substituted value.

摘要翻译： 提高了可变长度编码图像数据的解码处理速度。 图像处理器包括：可变长度解码单元，用于对输入数据进行可变长度解码并输出一对零系数的游程长度和非零系数; 逆量化单元，用于对非零系数进行逆量化，并获得要被输出的反量化数据; 地址设定单元，用于执行反向扫描，基于零系数的游程长度获得用于存储逆量化数据的地址，并指定数据存储单元中的地址; 写入信息存储单元，用于在对应于指定地址的地址中设置写入标志; 以及数据读取单元，用于从数据存储单元读取数据，并且基于存储在写入信息存储单元中的信息，直接从地址设置单元指定的地址输出数据，同时从地址替换预定值的数据 除了指定的地址以输出替代值。

公开(公告)号：US06310921B1

公开(公告)日：2001-10-30

申请号：US09055583

申请日：1998-04-06

申请人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

发明人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

IPC分类号： H04N712

CPC分类号： H04N19/90 ,  H04N5/4401 ,  H04N21/426 ,  H04N21/42607 ,  H04N21/42653 ,  H04N21/42692 ,  H04N21/4302 ,  H04N21/4341

摘要： A media processing apparatus is made up of an I/O processing unit for performing input/output processing which asynchronously occurs due to an external factor and a decode processing unit for performing decode processing mainly for decoding of data streams stored in a memory in parallel with the input/output processing. The input/output processing includes receiving the data streams which are asynchronously inputted, storing the inputted data streams in the memory, and supplying the data streams from the memory to the decode processing unit. The decode processing unit is made up of a sequential processing unit mainly performing condition judgements on the data streams and a routine processing unit performing decode processing on compressed video data aside from header analysis of the compressed video data in parallel with the sequential processing. Accordingly, the input/output processing means and the decode processing means are respectively charged with the asynchronous processing and the decode processing, and the input/output processing means and the decode processing means operate in parallel as in pipeline processing. As a result, the decode processing means can be devoted to the decode processing, regardless of asynchronous processing. Accordingly, processes including input processing of stream data, decode processing of the inputted data, and output processing of decoded data are executed efficiently.

摘要翻译： 媒体处理装置由用于执行由于外部因素而异步发生的输入/输出处理的I / O处理单元和用于执行主要用于解码存储在存储器中的数据流的解码处理的解码处理单元 输入/输出处理。 输入/输出处理包括接收异步输入的数据流，将输入的数据流存储在存储器中，并将数据流从存储器提供给解码处理单元。 解码处理单元由主要对数据流执行条件判断的顺序处理单元和与压缩视频数据的标题分析相一致的压缩视频数据执行解码处理的例程处理单元构成，与顺序处理并行。 因此，输入/输出处理装置和解码处理装置分别充有异步处理和解码处理，并且输入/输出处理装置和解码处理装置如在流水线处理中并行操作。 结果，无论异步处理如何，解码处理装置都可以用于解码处理。 因此，有效地执行包括流数据的输入处理，输入数据的解码处理和解码数据的输出处理的处理。