Invention Application
- Patent Title: Recessed-gate thin-film transistor with self-aligned lightly doped drain
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Application No.: US11513977Application Date: 2006-08-31
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Publication No.: US20080057649A1Publication Date: 2008-03-06
- Inventor: Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
- Applicant: Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
- Assignee: Sharp Laboratories of America, Inc.
- Current Assignee: Sharp Laboratories of America, Inc.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
Public/Granted literature
- US07419858B2 Recessed-gate thin-film transistor with self-aligned lightly doped drain Public/Granted day:2008-09-02
Information query
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