公开(公告)号：US20130009074A1

公开(公告)日：2013-01-10

申请号：US13596693

申请日：2012-08-28

Applicant: James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

Inventor： James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

IPC: H01L21/268

CPC classification number: B23K26/0622 ,  B23K26/0626 ,  B23K26/066 ,  G03F7/70041 ,  G03F7/70725 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. One method includes generating a sequence of excimer laser pulses, controllably modulating each pulse to a predetermined fluence, homoginizing each modulated pulse in a predetermined plane, masking portions of each homoginized pulse with a pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions corresponding to each fluence controlled patterned beamlet pulse, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets.

Abstract translation: 公开了将非晶硅薄膜样品加工成多晶硅薄膜的方法。 一种方法包括产生准分子激光脉冲序列，可控制地将每个脉冲调制到预定的注量，在每个调制脉冲在预定的平面上均匀化，每个同质化脉冲的部分用狭缝的图案掩蔽，以产生一系列流量控制脉冲的脉冲 图案化的子束，狭缝图案中的每个狭缝足够窄以防止在由对应于狭缝的子束照射的硅薄膜样品的区域中引起显着的成核，用能量控制狭缝的顺序照射非晶硅薄膜样品 图案化的子束以实现对应于每个注量控制的图案化子束脉冲的部分的熔化，并且可控地依次平移样品相对于狭缝图案化的子束的每个注量控制脉冲的相对位置。

公开(公告)号：US07923310B2

公开(公告)日：2011-04-12

申请号：US11779220

申请日：2007-07-17

Applicant: Mark A. Crowder ,  Yutaka Takafuji

Inventor： Mark A. Crowder ,  Yutaka Takafuji

IPC: H01L21/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/055 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/938

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped.

Abstract translation: 提供了用于核 - 壳 - 壳（CSS）纳米线晶体管（NWT）的制造方法。 该方法提供了具有半导体芯，绝缘体壳和导电壳的圆柱形CSS纳米结构。 CSS纳米结构具有覆盖衬底表面的较低的半圆柱体。 第一绝缘膜被保形地沉积在CSS纳米结构和各向异性等离子体蚀刻上。 在纳米结构较低的半圆柱体附近形成绝缘折痕桁条。 导电膜被共形沉积，并且选择的区域是各向异性等离子体蚀刻，在CSS纳米结构的中心部分形成覆盖栅电极的导电膜栅极带。 各向同性蚀刻除去邻近CSS纳米结构的中心部分的绝缘折返桁条，并且执行覆盖S / D区域的导电壳体的各向同性蚀刻。 屏幕氧化物层沉积在CSS纳米结构上。 在CS纳米结构侧面的末端部分的源极/漏极（S / D）区域被掺杂。

公开(公告)号：US20100252813A1

公开(公告)日：2010-10-07

申请号：US11779220

申请日：2007-07-17

Applicant: Mark A. Crowder ,  Yutaka Takafuji

Inventor： Mark A. Crowder ,  Yutaka Takafuji

IPC: H01L29/775 ,  H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6675 ,  H01L29/78621 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/055 ,  Y10S438/962 ,  Y10S977/773 ,  Y10S977/774 ,  Y10S977/938

Abstract: A fabrication method is provided for a core-shell-shell (CSS) nanowire transistor (NWT). The method provides a cylindrical CSS nanostructure with a semiconductor core, an insulator shell, and a conductive shell. The CSS nanostructure has a lower hemicylinder overlying a substrate surface. A first insulating film is conformally deposited overlying the CSS nanostructure and anisotropically plasma etched. Insulating reentrant stringers are formed adjacent the nanostructure lower hemicylinder. A conductive film is conformally deposited and selected regions are anisotropically plasma etched, forming conductive film gate straps overlying a gate electrode in a center section of the CSS nanostructure. An isotropically etching removes the insulating reentrant stringers adjacent the center section of the CSS nanostructure, and an isotropically etching of the conductive shell overlying the S/D regions is performed. A screen oxide layer is deposited over the CSS nanostructure. The source/drain (S/D) regions in end sections of the CS nanostructure flanking are doped.

Abstract translation: 提供了用于核 - 壳 - 壳（CSS）纳米线晶体管（NWT）的制造方法。 该方法提供了具有半导体芯，绝缘体壳和导电壳的圆柱形CSS纳米结构。 CSS纳米结构具有覆盖衬底表面的较低的半圆柱体。 第一绝缘膜被保形地沉积在CSS纳米结构和各向异性等离子体蚀刻上。 在纳米结构较低的半圆柱体附近形成绝缘折痕桁条。 导电膜被共形沉积，并且选择的区域是各向异性等离子体蚀刻，在CSS纳米结构的中心部分形成覆盖栅电极的导电膜栅极带。 各向同性蚀刻除去邻近CSS纳米结构的中心部分的绝缘折返桁条，并且执行覆盖S / D区域的导电壳体的各向同性蚀刻。 屏幕氧化物层沉积在CSS纳米结构上。 在CS纳米结构侧面的末端部分的源极/漏极（S / D）区域被掺杂。

公开(公告)号：US20080057649A1

公开(公告)日：2008-03-06

申请号：US11513977

申请日：2006-08-31

Applicant: Paul J. Schuele ,  Mark A. Crowder ,  Apostolos T. Voutsas ,  Hidayat Kisdarjono

Inventor： Paul J. Schuele ,  Mark A. Crowder ,  Apostolos T. Voutsas ,  Hidayat Kisdarjono

IPC: H01L21/336

CPC classification number: H01L29/78621 ,  H01L29/66621 ,  H01L29/66757 ,  H01L29/78627

Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

公开(公告)号：US07029996B2

公开(公告)日：2006-04-18

申请号：US10294001

申请日：2002-11-13

Applicant: James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

Inventor： James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

IPC: H01L21/20

CPC classification number: B23K26/0622 ,  B23K26/0626 ,  B23K26/066 ,  G03F7/70041 ,  G03F7/70725 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homoginized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

Abstract translation: 公开了将非晶硅薄膜样品加工成多晶硅薄膜的方法。 在一个优选的布置中，一种方法包括以下步骤：产生准分子激光脉冲序列，可控制地将序列中的每个准分子激光脉冲调制成预定的注量，在预定的平面中使序列中的每个调制的激光脉冲均匀化， 均匀注入能量密度控制的激光脉冲具有二维图案的狭缝，以产生线图案化子束的注量控制脉冲序列，狭缝图案中的每个狭缝足够窄，以防止在硅薄层区域中引起显着成核 通过对应于狭缝的子束照射的薄膜样品，以可控流程控制的狭缝图案化子束的顺序照射非晶硅薄膜样品，以按照图案化子束的脉冲序列对应于每个注量控制的图案化子束脉冲的部分进行熔化， 并可控地顺序地翻译一个关系 相对于狭缝图案化子束的每个注量控制脉冲的样品的位置，从而将非晶硅薄膜样品处理成单个或多晶硅薄膜。

公开(公告)号：US06635554B1

公开(公告)日：2003-10-21

申请号：US09816265

申请日：2001-03-23

Applicant: James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

Inventor： James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

IPC: C30B2120

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02678 ,  H01L21/2026

Abstract: System and methods for processing an amorphous silicon thin film sample into a single or polycrystalline silicon thin film are disclosed. The system includes an excimer laser for generating a plurality of excimer laser pulses of a predetermined fluence, an energy density modulator for controllably modulating fluence of the excimer laser pulses, a beam homoginizer for homoginizing modulated laser pulses in a predetermined plane, a mask for masking portions of the homoginized modulated laser pulses into patterned beamlets, a sample stage for receiving the patterned beamlets to effect melting of portions of any amorphous silicon thin film sample placed thereon corresponding to the beamlets, translating means for controllably translating a relative position of the sample stage with respect to a position of the mask and a computer for controlling the controllable fluence modulation of the excimer laser pulses and the controllable relative positions of the sample stage and mask, and for coordinating excimer pulse generation and fluence modulation with the relative positions of the sample stage and mask, to thereby process amorphous silicon thin film sample into a single or polycrystalline silicon thin film by sequential translation of the sample stage relative to the mask and irradiation of the sample by patterned beamlets of varying fluence at corresponding sequential locations thereon.

Abstract translation: 公开了将非晶硅薄膜样品加工成单个或多晶硅薄膜的系统和方法。 该系统包括用于产生预定能量密度的多个准分子激光脉冲的准分子激光器，用于可控地调制准分子激光脉冲的注量的能量密度调制器，用于在预定平面中均匀化调制的激光脉冲的光束均质器，用于掩蔽的掩模 将均质化的调制的激光脉冲的部分转换成图案化的子束，用于接收图案化的子束以实现对应于子束放置在其上的任何非晶硅薄膜样品的部分熔化的样品台，用于可控地平移样品台的相对位置的平移装置 相对于掩模的位置和用于控制准分子激光脉冲的可控注量调制和样品级和掩模的可控相对位置的计算机，并且用于将准分子脉冲产生和注量调制与样品的相对位置协调 舞台和面具，从而处理爱人 光硅薄膜样品通过样品台相对于掩模的顺序平移和通过在其上的相应顺序位置处具有变化的能量密度的图案化的子束照射样品而变成单个或多晶硅薄膜。

公开(公告)号：US08680427B2

公开(公告)日：2014-03-25

申请号：US12419821

申请日：2009-04-07

Applicant: James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

Inventor： James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

IPC: B23K26/00 ,  H01L29/04

CPC classification number: B23K26/0622 ,  B23K26/0626 ,  B23K26/066 ,  G03F7/70041 ,  G03F7/70725 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04

Abstract: A device on a supporting substrate is provided including a semiconductor film, having two or more rectangular crystalline regions spaced from each other, wherein each of the two or more rectangular crystalline regions comprises one single crystal region. The device can further include two or more thin-film transistors, wherein each of the two or more thin-film transistors comprises one or more active-channel regions. Each of the one or more active-channel regions can comprise at least one of said two or more rectangular crystalline regions. The device can further include an integrated circuit which comprises of the two or more thin-film transistors.

Abstract translation: 提供了一种在支撑基板上的装置，包括具有两个或更多个彼此间隔开的矩形晶体区域的半导体膜，其中两个或更多个矩形结晶区域中的每一个包括一个单晶区域。 该器件还可以包括两个或更多个薄膜晶体管，其中两个或更多个薄膜晶体管中的每一个包括一个或多个有源沟道区。 一个或多个有源沟道区中的每一个可以包括所述两个或更多个矩形晶体区域中的至少一个。 该器件还可以包括由两个或更多个薄膜晶体管组成的集成电路。

公开(公告)号：US07935599B2

公开(公告)日：2011-05-03

申请号：US11732675

申请日：2007-04-04

Applicant: Mark A. Crowder ,  Yutaka Takafuji

Inventor： Mark A. Crowder ,  Yutaka Takafuji

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method is provided for removing reentrant stringers in the fabrication of a nanowire transistor (NWT). The method provides a cylindrical nanostructure with an outside surface axis overlying a substrate surface. The nanostructure includes an insulated semiconductor core. A conductive film is conformally deposited overlying the nanostructure, to function as a gate strap or a combination gate and gate strap. A hard mask insulator is deposited overlying the conductive film and selected regions of the hard mask are anisotropically plasma etched. As a result, a conductive film gate electrode is formed substantially surrounding a cylindrical section of nanostructure. Inadvertently, conductive film reentrant stringers may be formed adjacent the nanostructure outside surface axis, made from the conductive film. The method etches, and so removes the conductive film reentrant stringers.

Abstract translation: 提供了一种用于在制造纳米线晶体管（NWT）中去除可折入桁条的方法。 该方法提供了一种圆柱形纳米结构，其外表面轴线覆盖在基底表面上。 纳米结构包括绝缘半导体芯。 导电膜共形沉积在纳米结构上方，用作栅极带或组合栅极和栅极带。 沉积覆盖导电膜的硬掩模绝缘体，硬掩模的选定区域是各向异性等离子体蚀刻。 结果，基本上围绕纳米结构的圆柱形部分形成导电膜栅电极。 无意中，可以形成与由导电膜制成的外表面轴线附近的导电膜折入桁条。 该方法蚀刻，因此去除导电膜可折入桁条。

公开(公告)号：US07872309B2

公开(公告)日：2011-01-18

申请号：US12140017

申请日：2008-06-16

Applicant: Paul J. Schuele ,  Mark A. Crowder ,  Apostolos T. Voutsas ,  Hidayat Kisdarjono

Inventor： Paul J. Schuele ,  Mark A. Crowder ,  Apostolos T. Voutsas ,  Hidayat Kisdarjono

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L29/78621 ,  H01L29/66621 ,  H01L29/66757 ,  H01L29/78627

Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.

Abstract translation: 提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。 该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。 沟槽有一个底部和侧壁。 在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。 然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。 替代地，LDD长度与沟槽的深度直接相关。

公开(公告)号：US07679028B2

公开(公告)日：2010-03-16

申请号：US11744493

申请日：2007-05-04

Applicant: James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

Inventor： James S. Im ,  Robert S. Sposili ,  Mark A. Crowder

IPC: B23K26/00 ,  B23K26/06

CPC classification number: B23K26/0622 ,  B23K26/0626 ,  B23K26/066 ,  G03F7/70041 ,  G03F7/70725 ,  H01L21/02532 ,  H01L21/0268 ,  H01L21/02686 ,  H01L21/02691 ,  H01L27/1285 ,  H01L27/1296 ,  H01L29/04

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, homoginizing each modulated laser pulse in the sequence in a predetermined plane, masking portions of each homoginized fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, each slit in the pattern of slits being sufficiently narrow to prevent inducement of significant nucleation in region of a silicon thin film sample irradiated by a beamlet corresponding to the slit, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof corresponding to each fluence controlled patterned beamlet pulse in the sequence of pulses of patterned beamlets, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

Abstract translation: 公开了将非晶硅薄膜样品加工成多晶硅薄膜的方法。 在一个优选的布置中，一种方法包括以下步骤：产生准分子激光脉冲序列，可控制地将序列中的每个准分子激光脉冲调制成预定的注量，在预定的平面中使序列中的每个调制的激光脉冲均匀化， 均匀注入能量密度控制的激光脉冲具有两维狭缝图案的序列，以产生线图案化子束的注量控制脉冲序列，狭缝图案中的每个狭缝足够窄以防止在硅薄层区域中引起显着成核 通过对应于狭缝的子束照射的薄膜样品，以可控流程控制的狭缝图案化子束的顺序照射非晶硅薄膜样品，以按照图案化子束的脉冲序列对应于每个注量控制的图案化子束脉冲的部分进行熔化， 并可控地顺序地翻译一个关系 相对于狭缝图案化子束的每个注量控制脉冲的样品的位置，从而将非晶硅薄膜样品处理成单个或多晶硅薄膜。