发明申请
- 专利标题: Memory array having an interconnect and method of manufacture
- 专利标题(中): 具有互连和制造方法的存储器阵列
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申请号: US11525547申请日: 2006-09-22
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公开(公告)号: US20080074927A1公开(公告)日: 2008-03-27
- 发明人: Franz Hofmann , Michael Specht , Nicolas Nagel , Josef Willer
- 申请人: Franz Hofmann , Michael Specht , Nicolas Nagel , Josef Willer
- 主分类号: G11C16/04
- IPC分类号: G11C16/04
摘要:
A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells, including a first memory cell and a last memory cell. A first interconnect is coupled to a first bit line and to each of the first, second, third and fourth memory cell strings. The first interconnect includes first, second, third and fourth string input select gates. Each input select gate has a first terminal coupled to the first bit line, and a second terminal coupled to one of the respective first, second, third or fourth memory cell strings.