A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; exposing a plurality of pads on the chips of the wafer; forming bumps on the pads of the chips of the wafer; performing tests from the bumps on the chips of the wafer. Alternatively, the present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; connecting a plurality of pads on the chips of the wafer to a plurality of corresponding pads on the substrate layer; planting bumps on the pads on the opposite side of the substrate layer; performing tests from the bumps on the substrate layer.