公开(公告)号：US07476555B2

公开(公告)日：2009-01-13

申请号：US11599473

申请日：2006-11-15

申请人： Wen Tsay ,  Bao-Iai Hwang ,  David Y Chang ,  Ling Huang

发明人： Wen Tsay ,  Bao-Iai Hwang ,  David Y Chang ,  Ling Huang

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L23/3114 ,  H01L22/20 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; exposing a plurality of pads on the chips of the wafer; forming bumps on the pads of the chips of the wafer; performing tests from the bumps on the chips of the wafer. Alternatively, the present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; connecting a plurality of pads on the chips of the wafer to a plurality of corresponding pads on the substrate layer; planting bumps on the pads on the opposite side of the substrate layer; performing tests from the bumps on the substrate layer.

摘要翻译： 一种芯片制造方法，包括设计阶段; 仿真阶段; 铸造阶段 测试/包装阶段; 切割阶段 和最后的涂装阶段。 本发明提供了一种芯片测试方法，包括在具有多个芯片的晶片上设置衬底层; 在晶片的芯片上暴露多个焊盘; 在晶片的芯片的焊盘上形成凸块; 从晶片的芯片上的凸块进行测试。 或者，本发明提供一种芯片测试方法，包括：在具有多个芯片的晶片上设置衬底层; 将所述晶片的芯片上的多个焊盘连接到所述衬底层上的多个相应焊盘; 在衬底层的相对侧的衬垫上种植凸起; 从衬底层上的凸起进行测试。

公开(公告)号：US20080113457A1

公开(公告)日：2008-05-15

申请号：US11599473

申请日：2006-11-15

申请人： Wen Tsay ,  Bao-Iai Hwang ,  David Y. Chang ,  Ling Huang

发明人： Wen Tsay ,  Bao-Iai Hwang ,  David Y. Chang ,  Ling Huang

IPC分类号： H01L21/66

CPC分类号： H01L23/3114 ,  H01L22/20 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method of chip manufacturing, comprises of a design stage; a simulation stage; a foundry stage; a testing/packaging stage; a cutting stage; and a final coating stage. The present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; exposing a plurality of pads on the chips of the wafer; forming bumps on the pads of the chips of the wafer; performing tests from the bumps on the chips of the wafer. Alternatively, the present invention provides a method of chip testing comprises of disposing a substrate layer on a wafer having a plurality of chips; connecting a plurality of pads on the chips of the wafer to a plurality of corresponding pads on the substrate layer; planting bumps on the pads on the opposite side of the substrate layer; performing tests from the bumps on the substrate layer.

摘要翻译： 一种芯片制造方法，包括设计阶段; 仿真阶段; 铸造阶段 测试/包装阶段; 切割阶段 和最后的涂装阶段。 本发明提供了一种芯片测试方法，包括在具有多个芯片的晶片上设置衬底层; 在晶片的芯片上暴露多个焊盘; 在晶片的芯片的焊盘上形成凸块; 从晶片的芯片上的凸块进行测试。 或者，本发明提供一种芯片测试方法，包括：在具有多个芯片的晶片上设置衬底层; 将所述晶片的芯片上的多个焊盘连接到所述衬底层上的多个相应焊盘; 在衬底层的相对侧的衬垫上种植凸起; 从衬底层上的凸起进行测试。