发明申请
- 专利标题： WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE
- 专利标题（中）： 具有良好CTE性能的WAFER LEVEL PACKAGE
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申请号： US11609970申请日： 2006-12-13
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公开(公告)号： US20080142946A1公开(公告)日： 2008-06-19
- 发明人: Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- 申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- 专利权人： Advanced Chip Engineering Technology Inc.
- 当前专利权人： Advanced Chip Engineering Technology Inc.
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/56
摘要：
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.
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