发明申请
- 专利标题： Methods and Apparatus for Dynamic Frequency Scaling of Phase Locked Loops for Microprocessors
- 专利标题（中）： 用于微处理器的锁相环的动态频率缩放的方法和装置
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申请号： US11624995申请日： 2007-01-19
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公开(公告)号： US20080174373A1公开(公告)日： 2008-07-24
- 发明人: Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
- 申请人： Liang Dai , Brandon Wayne Lewis , Jeffrey Todd Bridges , Weihua Chen
- 主分类号： H03L7/099
- IPC分类号： H03L7/099 ; H03L7/08
摘要：
A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
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