公开(公告)号：US09128720B2

公开(公告)日：2015-09-08

申请号：US13183129

申请日：2011-07-14

申请人： Gerald Paul Michalak ,  Jeffrey Todd Bridges

发明人： Gerald Paul Michalak ,  Jeffrey Todd Bridges

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3296 ,  G06F1/26 ,  Y02D10/172

摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.

摘要翻译： 提供了电压缩放的方法和装置。 在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。 时钟频率和电源电压可以在一段持续时间内保持基本上恒定。 如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。 变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。 确定运行极限后，将电源电压调整到运行极限内。

公开(公告)号：US08639943B2

公开(公告)日：2014-01-28

申请号：US12485089

申请日：2009-06-16

申请人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

发明人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06F12/145 ,  G06F12/1027 ,  G06F21/52 ,  G06F21/54 ,  G06F21/575 ,  G06F21/629 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/81 ,  G06F2221/2105 ,  G06F2221/2141

摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.

摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

公开(公告)号：US20110241423A1

公开(公告)日：2011-10-06

申请号：US12752515

申请日：2010-04-01

申请人： Jeffrey Todd Bridges ,  Sanjay B. Patel

发明人： Jeffrey Todd Bridges ,  Sanjay B. Patel

IPC分类号： H02J1/00

CPC分类号： G06F1/305 ,  Y10T307/406

摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.

摘要翻译： 公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。 在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。 当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。 当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。 以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

公开(公告)号：US20110140752A1

公开(公告)日：2011-06-16

申请号：US12637321

申请日：2009-12-14

申请人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

发明人： Manish Garg ,  Chiaming Chai ,  Jeffrey Todd Bridges

IPC分类号： H03K3/00

CPC分类号： H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).

摘要翻译： 公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。 在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。 时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。 反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。 输入信号可用于向功能电路提供时钟信号。

公开(公告)号：US07725625B2

公开(公告)日：2010-05-25

申请号：US12179970

申请日：2008-07-25

申请人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

发明人： Kenneth Alan Dockser ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Robert Douglas Clancy ,  Thomas Andrew Sartorius

IPC分类号： G06F3/00

CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

摘要翻译： 来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。 源端计数器跟踪FIFO中可用的空间。 在公开的示例中，初始计数器值对应于FIFO深度。 响应于来自源域的数据就绪信号，计数器无延迟地递减。 响应于来自接收器域的信令从FIFO读取数据，计数器递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器指示FIFO已满时，源可能再发送一次数据。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

公开(公告)号：US07568070B2

公开(公告)日：2009-07-28

申请号：US11193547

申请日：2005-07-29

申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

IPC分类号： G06F9/34

CPC分类号： G06F9/30149 ,  G06F9/3816 ,  G06F9/382

摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.

摘要翻译： 固定数量的可变长度指令存储在指令高速缓存的每一行中。 可变长度指令沿预定边界排列。 由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。 在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

公开(公告)号：US07426626B2

公开(公告)日：2008-09-16

申请号：US11210526

申请日：2005-08-23

申请人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00

CPC分类号： G06F12/1027 ,  G06F12/126 ,  G06F2212/681

摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

摘要翻译： 处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。 处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。 当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有的条目。 响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。 类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

公开(公告)号：US07415638B2

公开(公告)日：2008-08-19

申请号：US10995858

申请日：2004-11-22

申请人： Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F11/00 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/382

摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

摘要翻译： 在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。 相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。 特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。 这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。 然后重新获取的指令被正确预解码，写入高速缓存并执行。

公开(公告)号：US20080189521A1

公开(公告)日：2008-08-07

申请号：US12105091

申请日：2008-04-17

申请人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Victor Roberts Augsburg ,  Jeffrey Todd Bridges ,  Michael Scott Mcilvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/312

CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3851

摘要： A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.

摘要翻译： 一种用于优化微处理器中能够同时处理多个指令线程的吞吐量的方法。 在输入缓冲器和微处理器的流水线之间提供指令发生逻辑。 指令问题逻辑根据当指令到达要求管道中的阶段时所需操作数将可用的概率推测性地发出给定线程的指令。 如果当前流水线条件表明指令需要在共享资源中停止以等待操作数的重要概率，则指令的发出被阻止。 一旦指令停顿的概率低于某个阈值，则根据当前流水线条件，允许发出指令。

公开(公告)号：US20080174373A1

公开(公告)日：2008-07-24

申请号：US11624995

申请日：2007-01-19

申请人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

发明人： Liang Dai ,  Brandon Wayne Lewis ,  Jeffrey Todd Bridges ,  Weihua Chen

IPC分类号： H03L7/099 ,  H03L7/08

CPC分类号： H03L7/189 ,  H03L2207/06

摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

摘要翻译： 公开了一种采用多个振荡器复合器的锁相环。 锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。 锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。