A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w1 and write_w1 signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_w1 signal and an output for outputting a delayed version of the write_w1 signal. The wordline signal is activated by the wordline decoder based on the read_w1 signal and the delayed write_w1 signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.