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1.发明申请公开(公告)号：US20080117695A1
公开(公告)日：2008-05-22
申请号：US11560428
申请日：2006-11-16
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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2.发明申请Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays 审中-公开Domino SRAM数组中不平衡读/写路径的延迟机制公开(公告)号：US20080212396A1
公开(公告)日：2008-09-04
申请号：US12098715
申请日：2008-04-07
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w1 and write_w1 signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_w1 signal and an output for outputting a delayed version of the write_w1 signal. The wordline signal is activated by the wordline decoder based on the read_w1 signal and the delayed write_w1 signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_w 1和write_w 1信号由字线解码器基于在下一个周期是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_w 1信号的输入的缓冲器和用于输出write_w 1信号的延迟版本的输出。 字线信号由字线解码器基于read_w 1信号和延迟的write_w 1信号激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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3.发明授权公开(公告)号：US07400550B2
公开(公告)日：2008-07-15
申请号：US11560428
申请日：2006-11-16
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_wl and write_wl signals are generated by the wordline decoder based on whether a read or a write operation is to be performed in the next cycle. The wordline decoder includes a buffer having an input for receiving the write_wl signal and an output for outputting a delayed version of the write_wl signal. The wordline signal is activated by the wordline decoder based on the read_wl signal and the delayed write_wl signal. This overcomes the “early read” problem in which write performance is degraded due to a fast read path.
摘要翻译： 存储器系统，例如多米诺骨牌静态随机存取存储器（SRAM），包括多个存储器单元和通过字线耦合到存储器单元的字线解码器。 字线解码器通过字线向一个或多个存储器单元提供字线信号，以允许访问存储器单元用于读取操作或写入操作。 Read_wl和write_wl信号由字线解码器基于在下一周期中是执行读操作还是写操作生成。 字线解码器包括具有用于接收write_wl信号的输入的缓冲器和用于输出write_wl信号的延迟版本的输出。 基于read_wl信号和延迟的write_wl信号，字线信号由字线解码器激活。 这克服了由于快速读取路径而导致写入性能下降的“早期读取”问题。
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公开(公告)号：US07206236B1
公开(公告)日：2007-04-17
申请号：US11330693
申请日：2006-01-12
申请人： Anthony Gus Aipperspach , Todd Alan Christensen , Elizabeth Lair Gerhard , George Francis Paulik
发明人： Anthony Gus Aipperspach , Todd Alan Christensen , Elizabeth Lair Gerhard , George Francis Paulik
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.
摘要翻译： 使用冗余位线修复具有多个独立故障的诸如SRAM，DRAM，CAM和可编程ROM的阵列。 第一实施例在阵列的一侧提供冗余位线。 在写入期间，数据将朝着阵列一侧的冗余位线移动，绕过故障位线。 第二实施例在阵列的每一侧提供备用位线。 在写入期间，第一故障位线由阵列的第一侧上的第一备用位线替代，并且第二故障位线被阵列的第二侧上的第二备用位线替代。
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