发明申请
- 专利标题： WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE
- 专利标题（中）： 具有良好CTE性能的WAFER LEVEL PACKAGE
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申请号： US12141138申请日： 2008-06-18
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公开(公告)号： US20080248614A1公开(公告)日： 2008-10-09
- 发明人: Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- 申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
- 专利权人： Advanced Chip Engineering Technology Inc.
- 当前专利权人： Advanced Chip Engineering Technology Inc.
- 主分类号： H01L21/58
- IPC分类号： H01L21/58
摘要：
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
公开/授权文献
- US07655501B2 Wafer level package with good CTE performance 公开/授权日：2010-02-02
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