发明申请
- 专利标题： Method of shield line placement for semiconductor integrated circuit, design apparatus for semiconductor integrated circuit, and design program for semiconductor integrated circuit
- 专利标题（中）： 半导体集成电路屏蔽线放置方法，半导体集成电路设计装置及半导体集成电路设计程序
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申请号： US12216377申请日： 2008-07-02
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公开(公告)号： US20080276213A1公开(公告)日： 2008-11-06
- 发明人: Katsushi Aoki , Takahiro Toda , Junya Yamasaki , Shinichi Iida , Hiroki Murakami
- 申请人： Katsushi Aoki , Takahiro Toda , Junya Yamasaki , Shinichi Iida , Hiroki Murakami
- 申请人地址： JP Kawasaki
- 专利权人： FUJITSU LIMITED
- 当前专利权人： FUJITSU LIMITED
- 当前专利权人地址： JP Kawasaki
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a shield wiring unit which, when the placement of the signal line is changed, changes in interlinking fashion with the changed placement the placement of the shield line that is associated with the signal line by the association information.