公开(公告)号：US20080276213A1

公开(公告)日：2008-11-06

申请号：US12216377

申请日：2008-07-02

申请人： Katsushi Aoki ,  Takahiro Toda ,  Junya Yamasaki ,  Shinichi Iida ,  Hiroki Murakami

发明人： Katsushi Aoki ,  Takahiro Toda ,  Junya Yamasaki ,  Shinichi Iida ,  Hiroki Murakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a shield wiring unit which, when the placement of the signal line is changed, changes in interlinking fashion with the changed placement the placement of the shield line that is associated with the signal line by the association information.

摘要翻译： 一种半导体集成电路设计装置，包括：关联信息创建单元，其创建用于将信号线的布线信息与放置在信号线上的屏蔽线的布线信息相关联的关联信息; 存储由此创建的关联信息的关联信息存储单元; 以及屏蔽布线单元，当信号线的布置改变时，通过关联信息，与信号线相关联的屏蔽线的布置与改变的布置相互连接地改变。

公开(公告)号：US07810052B2

公开(公告)日：2010-10-05

申请号：US11785897

申请日：2007-04-20

申请人： Katsushi Aoki ,  Junya Yamasaki ,  Hiroki Murakami

发明人： Katsushi Aoki ,  Junya Yamasaki ,  Hiroki Murakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A logical-group creating unit creates a logical group from a cell included in a selected range of a logical drawing that is specified in a logical page. A logical-group extracting unit extracts a same/similar logical group by determining whether logical drawings of created logical groups are same or similar to each other. A pattern creating unit creates an implementation pattern of a logical group included in extracted same/similar logical group.

摘要翻译： 逻辑组创建单元从在逻辑页面中指定的逻辑绘图的选定范围中包括的单元创建逻辑组。 逻辑组提取单元通过确定所创建的逻辑组的逻辑图是否相同或相似来提取相同/相似的逻辑组。 模式创建单元创建包括在提取的相同/相似的逻辑组中的逻辑组的实现模式。

公开(公告)号：US20080028356A1

公开(公告)日：2008-01-31

申请号：US11785897

申请日：2007-04-20

申请人： Katsushi Aoki ,  Junya Yamasaki ,  Hiroki Murakami

发明人： Katsushi Aoki ,  Junya Yamasaki ,  Hiroki Murakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A logical-group creating unit creates a logical group from a cell included in a selected range of a logical drawing that is specified in a logical page. A logical-group extracting unit extracts a same/similar logical group by determining whether logical drawings of created logical groups are same or similar to each other. A pattern creating unit creates an implementation pattern of a logical group included in extracted same/similar logical group.

摘要翻译： 逻辑组创建单元从在逻辑页面中指定的逻辑绘图的选定范围中包括的单元创建逻辑组。 逻辑组提取单元通过确定所创建的逻辑组的逻辑图是否相同或相似来提取相同/相似的逻辑组。 模式创建单元创建包括在提取的相同/相似的逻辑组中的逻辑组的实现模式。

公开(公告)号：US07131086B2

公开(公告)日：2006-10-31

申请号：US10915608

申请日：2004-08-11

申请人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

发明人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic verification device comprises a data converter section adapted to convert real circuit data to be processed for designing a logic circuit into data for verification to be processed for logic verification and vice versa, a verifier section adapted to operate for logic verification of said data for verification and a temporary modifier section adapted to acquire the result of verification of said verifier section and the modification candidate data corresponding to the result of verification of said verifier section and pre-selected as candidate data for modification of said data for verification and modify said data for verification on the basis of said acquired result of verification and said acquired modification candidate data.

摘要翻译： 逻辑验证装置，逻辑验证方法和逻辑验证计算机程序，可以减少在设计逻辑电路时涉及的步骤数，特别是当设计的逻辑电路在检测到错误的位置进行逻辑验证和修改时。 逻辑验证装置包括：数据转换器部分，适于将待处理的实际电路数据转换为用于设计逻辑电路的数据以进行逻辑验证处理以进行验证，反之亦然;验证器部分，适于操作所述数据的逻辑验证 验证和临时修改器部分，其适于获取所述验证器部分的验证结果和对应于所述验证​​器部分的验证结果的修改候选数据，并且被预先选择作为用于修改所述数据进行验证的候选数据，并修改所述数据 用于基于所述获取的验证结果和所述获取的修改候选数据进行验证。

公开(公告)号：US20050229122A1

公开(公告)日：2005-10-13

申请号：US10915608

申请日：2004-08-11

申请人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

发明人： Junya Yamasaki ,  Sumiko Maeda ,  Kenya Takeyama ,  Yukio Makino

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A logic verification device, a logic verification method and a logic verification computer program that can reduce the number of steps involved in designing a logic circuit particularly when the designed logic circuit is subjected to logic verification and modification at the spot where an error is detected. The logic verification device comprises a data converter section adapted to convert real circuit data to be processed for designing a logic circuit into data for verification to be processed for logic verification and vice versa, a verifier section adapted to operate for logic verification of said data for verification and a temporary modifier section adapted to acquire the result of verification of said verifier section and the modification candidate data corresponding to the result of verification of said verifier section and pre-selected as candidate data for modification of said data for verification and modify said data for verification on the basis of said acquired result of verification and said acquired modification candidate data.

摘要翻译： 逻辑验证装置，逻辑验证方法和逻辑验证计算机程序，可以减少在设计逻辑电路时涉及的步骤数，特别是当设计的逻辑电路在检测到错误的位置进行逻辑验证和修改时。 逻辑验证装置包括：数据转换器部分，适于将待处理的实际电路数据转换为用于设计逻辑电路的数据以进行逻辑验证处理以进行验证，反之亦然;验证器部分，适于操作所述数据的逻辑验证 验证和临时修改器部分，其适于获取所述验证器部分的验证结果和对应于所述验证​​器部分的验证结果的修改候选数据，并且被预先选择作为用于修改所述数据进行验证的候选数据，并修改所述数据 用于基于所述获取的验证结果和所述获取的修改候选数据进行验证。

公开(公告)号：US08166443B2

公开(公告)日：2012-04-24

申请号：US12216377

申请日：2008-07-02

申请人： Katsushi Aoki ,  Takahiro Toda ,  Junya Yamasaki ,  Shinichi Iida ,  Hiroki Murakami

发明人： Katsushi Aoki ,  Takahiro Toda ,  Junya Yamasaki ,  Shinichi Iida ,  Hiroki Murakami

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit design apparatus includes: an association information creating unit which creates association information for associating wiring information of a signal line with wiring information of a shield line placed for the signal line; an association information storage unit which stores the thus created association information; and a shield wiring unit which, when the placement of the signal line is changed, changes in interlinking fashion with the changed placement the placement of the shield line that is associated with the signal line by the association information.

摘要翻译： 一种半导体集成电路设计装置，包括：关联信息创建单元，其创建用于将信号线的布线信息与放置在信号线上的屏蔽线的布线信息相关联的关联信息; 存储由此创建的关联信息的关联信息存储单元; 以及屏蔽布线单元，当信号线的布置改变时，通过关联信息，与信号线相关联的屏蔽线的布置与改变的布置相互连接地改变。