发明申请
- 专利标题: Stacked package structure and fabrication method thereof
- 专利标题(中): 堆叠封装结构及其制造方法
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申请号: US12152687申请日: 2008-05-16
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公开(公告)号: US20080283994A1公开(公告)日: 2008-11-20
- 发明人: Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
- 申请人: Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
- 申请人地址: TW Taichung
- 专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人: Siliconware Precision Industries Co., Ltd.
- 当前专利权人地址: TW Taichung
- 优先权: TW096117702 20070518
- 主分类号: H01L23/49
- IPC分类号: H01L23/49 ; H01L21/56
摘要:
A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.
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