发明申请
- 专利标题: Integrated circuit package for semiconductior devices with improved electric resistance and inductance
- 专利标题(中): 具有改善电阻和电感的半导体器件的集成电路封装
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申请号: US12215049申请日: 2008-06-23
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公开(公告)号: US20090014853A1公开(公告)日: 2009-01-15
- 发明人: Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
- 申请人: Leeshawn Luo , Anup Bhalla , Yueh-Se Ho , Sik K. Lui , Mike Chang
- 主分类号: H01L23/495
- IPC分类号: H01L23/495
摘要:
A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
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