- 专利标题： Low Power Circuit Structure with Metal Gate and High-k Dielectric
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申请号： US11835318申请日： 2007-08-07
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公开(公告)号： US20090039435A1公开(公告)日： 2009-02-12
- 发明人: Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri
- 申请人： Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/8238
摘要：
FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.
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