公开(公告)号：US09263276B2

公开(公告)日：2016-02-16

申请号：US12551292

申请日：2009-11-18

申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

公开(公告)号：US09059314B2

公开(公告)日：2015-06-16

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US09059211B2

公开(公告)日：2015-06-16

申请号：US13251471

申请日：2011-10-03

申请人： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

发明人： Michael P. Chudzik ,  Deleep R. Nair ,  Vijay Narayanan ,  Carl J. Radens ,  Jay M. Shah

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/66575 ,  H01L21/28017 ,  H01L21/283 ,  H01L21/823864 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78

摘要： At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.

公开(公告)号：US08878298B2

公开(公告)日：2014-11-04

申请号：US13346165

申请日：2012-01-09

申请人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L29/66795

摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。

公开(公告)号：US08835260B2

公开(公告)日：2014-09-16

申请号：US13547792

申请日：2012-07-12

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及 形成在高k电介质层上方的导电电极层。

公开(公告)号：US08748991B2

公开(公告)日：2014-06-10

申请号：US13550919

申请日：2012-07-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/513 ,  H01L29/78

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括具有大于约3.9的高介电常数的高k电介质，与高k电介质接合的锗（Ge）材料层，以及设置在高k电介质或Ge材料上方的导电电极层 层。 栅极堆叠优化了平带电压或阈值电压的偏移，以在p-FET器件中获得高性能。

公开(公告)号：US08735996B2

公开(公告)日：2014-05-27

申请号：US13547772

申请日：2012-07-12

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

摘要翻译： 提供半导体结构。 该结构包括半导体材料的半导体衬底和具有介电常数大于硅的介电常数介电层的栅极电介质。 栅极电介质位于半导体衬底上。 栅电极邻接栅极电介质。 栅电极包括邻接栅电介质的下金属层，邻接下金属层的扫除金属层，与清扫金属层邻接的上金属层和邻接上金属层的硅层。 清除金属层响应于退火而在上金属层和硅层之间的界面处减少氧化层。

公开(公告)号：US20140004695A1

公开(公告)日：2014-01-02

申请号：US13534573

申请日：2012-06-27

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L21/283

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

公开(公告)号：US20130175630A1

公开(公告)日：2013-07-11

申请号：US13345295

申请日：2012-01-06

申请人： Takashi ANDO ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi ANDO ,  Eduard A. Cartier ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L27/088 ,  H01L29/772 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

摘要： A transistor includes a semiconductor layer and a gate structure located on the semiconductor layer. The gate structure includes a first dielectric layer. The first dielectric layer includes a doped region and an undoped region below the doped region. A second dielectric layer is located on the first dielectric layer, and a first metal nitride layer is located on the second dielectric layer. The doped region of the first dielectric layer comprises dopants from the second dielectric layer. Source and drain regions in the semiconductor layer are located on opposite sides of the gate structure.

摘要翻译： 晶体管包括位于半导体层上的半导体层和栅极结构。 栅极结构包括第一介电层。 第一介电层包括掺杂区域和掺杂区域下面的未掺杂区域。 第二电介质层位于第一电介质层上，第一金属氮化物层位于第二电介质层上。 第一介电层的掺杂区域包括来自第二介电层的掺杂剂。 半导体层中的源极和漏极区位于栅极结构的相对侧上。

公开(公告)号：US20130134545A1

公开(公告)日：2013-05-30

申请号：US13306621

申请日：2011-11-29

申请人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

发明人： Terence B. Hook ,  Vijay Narayanan ,  Jay M. Shah ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Helen H. Wang ,  Chendong Zhu

IPC分类号： H01L29/06 ,  H01L21/28

CPC分类号： H01L21/28247 ,  H01L21/28123 ,  H01L21/76224

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括：高K电介质区域; 阻挡区域，其设置成抵抗高K电介质区域的至少一个表面，并且适于响应于暴露于氧气而形成氧化层; 以及设置在阻挡区域上的富氧区域，使得阻挡区域介于富氧区域和高K电介质区域之间。