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    Techniques for the fabrication of thick gate dielectric
    1.
    发明授权
    Techniques for the fabrication of thick gate dielectric 失效
    用于制造厚栅极电介质的技术

    公开(公告)号：US08778750B2

    公开(公告)日：2014-07-15

    申请号：US13464966

    申请日：2012-05-05

    申请人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    发明人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/76224

    摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

    摘要翻译： 一种制造CMOS器件的方法包括以下步骤。 提供晶片。 STI用于在晶片中形成至少一个有效区域。 氧化硅层沉积在覆盖有源区的晶片上。 第一高k材料沉积在氧化硅层上。 选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个 活跃区域。 在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。 还提供了CMOS器件。

    Low power circuit structure with metal gate and high-k dielectric
    3.
    发明授权
    Low power circuit structure with metal gate and high-k dielectric 失效
    具有金属栅极和高k电介质的低功率电路结构

    公开(公告)号：US07807525B2

    公开(公告)日：2010-10-05

    申请号：US12538186

    申请日：2009-08-10

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785

    摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

    摘要翻译： 公开了具有高k介质栅极绝缘体，含金属栅极和阈值调节盖层的PFET和NFET器件的FET器件结构。 NFET栅极堆叠和PFET栅极堆叠各自具有在NFET器件和PFET器件中相同的部分。 该相同部分至少包含栅极金属层和盖层。 由于相同的部分，器件制造被简化，需要减少数量的掩模。 此外，由于使用单层金属作为两种器件的栅极的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过高k电介质的氧气曝光进一步调节器件阈值。 阈值是针对低功耗设备操作的。

    Techniques for the Fabrication of Thick Gate Dielectric
    7.
    发明申请
    Techniques for the Fabrication of Thick Gate Dielectric 失效
    厚栅电介质制造技术

    公开(公告)号：US20130292778A1

    公开(公告)日：2013-11-07

    申请号：US13464966

    申请日：2012-05-05

    申请人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    发明人： Eduard Albert Cartier ,  Michael P. Chudzik ,  Andreas Kerber ,  Siddarth Krishnan ,  Naim Moumen

    IPC分类号： H01L27/092 ,  H01L21/76

    CPC分类号： H01L21/823857 ,  H01L21/76224

    摘要： A method for fabricating a CMOS device includes the following steps. A wafer is provided. STI is used to form at least one active area in the wafer. A silicon oxide layer is deposited onto the wafer covering the active area. A first high-k material is deposited onto the silicon oxide layer. Portions of the silicon oxide layer and the first high-k material are selectively removed, such that the silicon oxide layer and the first high-k material remain over one or more first regions of the active area and are removed from over one or more second regions of the active area. A second high-k material is deposited onto the first high-k material over the one or more first regions of the active area and onto a surface of the wafer in the one or more second regions of the active area. A CMOS device is also provided.

    摘要翻译： 一种制造CMOS器件的方法包括以下步骤。 提供晶片。 STI用于在晶片中形成至少一个有效区域。 氧化硅层沉积在覆盖有源区的晶片上。 第一高k材料沉积在氧化硅层上。 选择性地去除氧化硅层和第一高k材料的部分，使得氧化硅层和第一高k材料保留在有源区的一个或多个第一区上，并从一个或多个第二个 活跃区域。 在有源区域的一个或多个第一区域上并且在有源区域的一个或多个第二区域中的晶片的表面上沉积第二高k材料到第一高k材料上。 还提供了CMOS器件。

    Low Power Circuit Structure with Metal Gate and High-k Dielectric
    8.
    发明申请
    Low Power Circuit Structure with Metal Gate and High-k Dielectric 失效
    具有金属栅极和高k电介质的低功率电路结构

    公开(公告)号：US20090298245A1

    公开(公告)日：2009-12-03

    申请号：US12538186

    申请日：2009-08-10

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Parunchri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Parunchri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785

    摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

    摘要翻译： 公开了具有高k介质栅极绝缘体，含金属栅极和阈值调节盖层的PFET和NFET器件的FET器件结构。 NFET栅极堆叠和PFET栅极堆叠各自具有在NFET器件和PFET器件中相同的部分。 该相同部分至少包含栅极金属层和盖层。 由于相同的部分，器件制造被简化，需要减少数量的掩模。 此外，由于使用单层金属作为两种器件的栅极的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过高k电介质的氧气曝光进一步调节器件阈值。 阈值是针对低功耗设备操作的。

    Threshold Adjustment for High-K Gate Dielectric CMOS
    9.
    发明申请
    Threshold Adjustment for High-K Gate Dielectric CMOS 有权
    高K栅介质CMOS的阈值调整

    公开(公告)号：US20090291553A1

    公开(公告)日：2009-11-26

    申请号：US12535554

    申请日：2009-08-04

    申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Vijay Narayanan ,  Vamsi Paruchuri

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/28176 ,  H01L27/092 ,  H01L29/6656 ,  Y10S438/981

    摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

    摘要翻译： 公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。 该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。 结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。 本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。