发明申请
US20090040849A1 SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
失效
半导体存储器,半导体存储器和系统的测试方法
- 专利标题: SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
- 专利标题(中): 半导体存储器,半导体存储器和系统的测试方法
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申请号: US12127161申请日: 2008-05-27
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公开(公告)号: US20090040849A1公开(公告)日: 2009-02-12
- 发明人: Kaoru MORI , Jun OHNO , Hiroyuki KOBAYASHI
- 申请人: Kaoru MORI , Jun OHNO , Hiroyuki KOBAYASHI
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 优先权: JP2007-207041 20070808
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C8/00
摘要:
Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.
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