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    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM
    1.
    发明申请
    SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US20090040849A1

    公开(公告)日：2009-02-12

    申请号：US12127161

    申请日：2008-05-27

    申请人： Kaoru MORI ,  Jun OHNO ,  Hiroyuki KOBAYASHI

    发明人： Kaoru MORI ,  Jun OHNO ,  Hiroyuki KOBAYASHI

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/26 ,  G11C7/1045 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C2029/5006 ,  G11C2029/5602

    摘要： Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized.

    摘要翻译： 每个程序电路根据程序状态输出指示第一或第二操作规范的操作规范信号。 每个规格改变电路由相应的块选择信号设置，并输出指示第二操作规范的操作指定信号。 每个定时控制电路根据操作指定信号改变位线的预充电控制信号的输出定时。 通过来自规范改变电路的操作规范信号，在对程序电路进行编程之前可以在每个存储器块中检测到故障。 此后，程序电路可以解除故障。 可以通过块选择信号为每个存储器块设置预充电控制信号的输出定时，而不布线用于设置每个规格改变电路的专用信号线。 因此，可以使芯片尺寸的增加最小化。

    SCREEN SHARING APPARATUS, SCREEN SHARING METHOD AND SCREEN SHARING PROGRAM
    2.
    发明申请
    SCREEN SHARING APPARATUS, SCREEN SHARING METHOD AND SCREEN SHARING PROGRAM 审中-公开
    屏幕共享设备，屏幕共享方法和屏幕共享程序

    公开(公告)号：US20130241803A1

    公开(公告)日：2013-09-19

    申请号：US13795178

    申请日：2013-03-12

    申请人： Hiroyuki KOBAYASHI

    发明人： Hiroyuki KOBAYASHI

    IPC分类号： G06F3/14

    CPC分类号： G06F3/1454 ,  G06F3/0485 ,  G06F3/1462

    摘要： A screen reception apparatus according to an exemplary aspect of the invention includes, a block image information storage unit that stores therein a plurality of block images resulting from segmentation of an entire image which is scrolled by software so that a display area, which is part of the entire image, is displayed on a first screen, as well as identifications of the respective block images, such that the block images and the identifications are correlated with each other; and an on-screen display unit that receives one of the identifications and display location within the first screen reads out from the block image information storage unit one of the block images corresponding to the received identification and, display the read out block image at the display location within the first screen.

    摘要翻译： 根据本发明的示例性方面的屏幕接收装置包括：块图像信息存储单元，其存储由软件滚动的整个图像的分割产生的多个块图像，使得显示区域是作为 整个图像被显示在第一屏幕上，以及各个块图像的标识，使得块图像和标识相互关联; 并且接收第一屏幕中的一个标识和显示位置的屏幕显示单元从块图像信息存储单元中读出与接收到的标识相对应的块图像之一，并在显示器上显示读出的块图像 位于第一屏幕内。

    IMAGE SELECTION DEVICE AND IMAGE SELECTING METHOD
    3.
    发明申请
    IMAGE SELECTION DEVICE AND IMAGE SELECTING METHOD 有权
    图像选择装置和图像选择方法

    公开(公告)号：US20120249826A1

    公开(公告)日：2012-10-04

    申请号：US13493152

    申请日：2012-06-11

    申请人： Hiroyuki KOBAYASHI ,  Kimitaka MURASHITA ,  Masayoshi SHIMIZU ,  Takehiro NAKAI

    发明人： Hiroyuki KOBAYASHI ,  Kimitaka MURASHITA ,  Masayoshi SHIMIZU ,  Takehiro NAKAI

    IPC分类号： H04N5/228 ,  H04N5/14

    CPC分类号： H04N5/23293 ,  G06K9/036 ,  G06T7/0002 ,  G06T2207/10016 ,  G06T2207/30168 ,  H04N5/23248 ,  H04N5/23254 ,  H04N5/77

    摘要： An image selection device includes: an image acquiring unit which acquires a plurality of shot images acquired by continuously shooting a subject; an area segmentation unit which segments an image area of the shot image into a motion area indicating different positions by a specified amount or more between two shot images and a non-motion area other than the motion area based on the two consecutive shot images in time series in the plurality of shot images; and a selection unit which selects at least one shot image from the plurality of shot images based on an amount of blur of an image in the non-motion area.

    摘要翻译： 图像选择装置包括：图像获取单元，其获取通过连续拍摄被摄体而获取的多个拍摄图像; 区域分割单元，其基于时间上的两个连续拍摄图像，将拍摄图像的图像区域分割成指示不同位置的运动区域，其在两拍摄图像与运动区域之间的非运动区域之间指定量以上 系列在多个拍摄图像中; 以及选择单元，其基于所述非运动区域中的图像的模糊量，从所述多个拍摄图像中选择至少一个拍摄图像。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20110215872A1

    公开(公告)日：2011-09-08

    申请号：US12833634

    申请日：2010-07-09

    申请人： Hiroyuki KOBAYASHI

    发明人： Hiroyuki KOBAYASHI

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00

    摘要： A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency.

    摘要翻译： 半导体集成电路包括：数字控制振荡器; 相位数据输出单元; 一体化处理单元; 过滤器单元; 输出作为振荡器调谐字的乘法器（第一乘法器）将经过来自滤波器单元的时分的输出信号与预定系数相乘得到的值; 以及与参考频率同步地将振荡器调谐字分配给数字控制的振荡器的输出选择器（调谐字分离单元）。

    OSCILLATOR CONTROL APPARATUS
    7.
    发明申请
    OSCILLATOR CONTROL APPARATUS 失效
    振荡器控制装置

    公开(公告)号：US20100214028A1

    公开(公告)日：2010-08-26

    申请号：US12555178

    申请日：2009-09-08

    申请人： Hiroyuki KOBAYASHI

    发明人： Hiroyuki KOBAYASHI

    IPC分类号： H03L7/06

    CPC分类号： H03L7/08 ,  H03L2207/50

    摘要： An oscillator control apparatus has a digitally-controlled oscillator which outputs an oscillation signal having an oscillation frequency in response to an oscillator adjusting signal, a counter which counts the oscillation signal and outputs a count in response to a reference signal in synchronism with the oscillation signal, a time-to-digital converter which calculates a phase difference between the oscillation signal and the reference signal, an adder which adds the count and the phase difference and outputs the added value as first phase information, a corrector which corrects the first phase information in response to a phase control signal for setting an oscillation frequency of the digitally-controlled oscillator when a time difference between a rising-up timing of the oscillation signal and a rising-up timing of the reference signal is less than a predetermined time, and outputs second phase information, and a filter for smoothing a difference between the phase control signal and the second phase information, to output the oscillator adjusting signal.

    摘要翻译： 振荡器控制装置具有数字控制振荡器，其响应于振荡器调节信号输出具有振荡频率的振荡信号，对振荡信号进行计数的计数器，并响应于与振荡信号同步的参考信号输出计数 ，计算振荡信号和参考信号之间的相位差的时间数字转换器，将计数和相位差相加并输出相加值作为第一相位信息的加法器，校正第一相位信息的校正器 响应于当所述振荡信号的上升定时与所述参考信号的上升定时之间的时间差小于预定时间时，用于设置所述数字控制振荡器的振荡频率的相位控制信号，以及 输出第二相位信息，以及滤波器，用于平滑相位控制信号a之间的差 找出第二相信息，输出振荡器调整信号。

    COMMUNICATION SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    COMMUNICATION SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    通信半导体集成电路

    公开(公告)号：US20090190694A1

    公开(公告)日：2009-07-30

    申请号：US12356870

    申请日：2009-01-21

    申请人： Hiroyuki KOBAYASHI

    发明人： Hiroyuki KOBAYASHI

    IPC分类号： H04L27/12

    CPC分类号： H03C3/0941 ,  H03C3/095 ,  H03C3/0975

    摘要： A communication semiconductor integrated circuit, has: a first computing element which adds the count value and the phase difference value and outputs a first computed value as an addition result; a second computing element which adds set frequency data obtained by dividing a carrier frequency by a reference frequency of the reference signal and modulation frequency data obtained by dividing a modulation frequency by the reference frequency, and outputs a second computed value as an addition result; a third computing element which subtracts the second computed value from the first computed value and outputs a third computed value as a subtraction result, the third computed value being a phase error; and a fourth computing element which adds the carrier frequency control value and the modulation frequency control value, and outputs the oscillator tuning word as an addition result.

    摘要翻译： 通信半导体集成电路具有：第一计算单元，其将计数值和相位差值相加，并输出第一计算值作为相加结果; 将通过将载波频率除以参考信号的参考频率而获得的设置频率数据和通过将调制频率除以参考频率获得的调制频率数据的第二计算元件，并输出第二计算值作为相加结果; 第三计算元件，其从所述第一计算值中减去所述第二计算值，并输出第三计算值作为减法结果，所述第三计算值是相位误差; 以及第四计算单元，其添加载波频率控制值和调制频率控制值，并输出振荡器调谐字作为相加结果。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM 有权
    半导体集成电路与系统

    公开(公告)号：US20090161469A1

    公开(公告)日：2009-06-25

    申请号：US12343061

    申请日：2008-12-23

    申请人： Hiroyuki KOBAYASHI

    发明人： Hiroyuki KOBAYASHI

    IPC分类号： G11C7/00 ,  H03K3/00

    CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/10

    摘要： The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer circuit, that outputs a second output signal on receipt of the first input signal, and that outputs the second output signal based on a check signal; a third buffer circuit that outputs a third output signal based on the check signal; a determination circuit that receives the second output signal and the third output signal and activates a detection signal, in response to the detection that the second output signal is behind the third output signal; and a fourth buffer circuit that operates during the activation of the detection signal and outputs the third output signal to the output terminal, on receipt of the first input signal.

    摘要翻译： 半导体集成电路包括：第一缓冲电路，其在接收到第一输入信号时将第一输出信号输出到输出端; 第二缓冲电路，其包括具有与第一缓冲电路相似的配置的电路，其在接收到第一输入信号时输出第二输出信号，并且基于检查信号输出第二输出信号; 第三缓冲电路，其基于所述检查信号输出第三输出信号; 确定电路，响应于所述第二输出信号在所述第三输出信号之后的检测，接收所述第二输出信号和所述第三输出信号并激活检测信号; 以及第四缓冲电路，其在激活检测信号期间操作，并且在接收到第一输入信号时将第三输出信号输出到输出端。