- 专利标题： FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL
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申请号： US12200930申请日： 2008-08-28
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公开(公告)号： US20090052248A1公开(公告)日： 2009-02-26
- 发明人: Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- 申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
- 申请人地址： US CA Sunnyvale
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 主分类号： G11C16/34
- IPC分类号： G11C16/34 ; G11C16/06 ; G11C29/00
摘要：
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
公开/授权文献
- US07778080B2 Flash memory array system including a top gate memory cell 公开/授权日：2010-08-17