公开(公告)号：US08804429B2

公开(公告)日：2014-08-12

申请号：US13315213

申请日：2011-12-08

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

摘要： A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

摘要翻译： 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

公开(公告)号：US08674749B2

公开(公告)日：2014-03-18

申请号：US12726249

申请日：2010-03-17

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu AAron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu AAron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07 ,  H02M1/36 ,  H02M1/44

摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

公开(公告)号：US20130187707A1

公开(公告)日：2013-07-25

申请号：US13726522

申请日：2012-12-24

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

IPC分类号： G05F3/02

CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

摘要翻译： 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

公开(公告)号：US20130107632A1

公开(公告)日：2013-05-02

申请号：US13286969

申请日：2011-11-01

申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC分类号： G11C5/14 ,  G05F3/02

CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.

摘要翻译： 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 检测来自第二管芯焊盘的电流的电路在集成电路管芯中。 开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

公开(公告)号：US20130106391A1

公开(公告)日：2013-05-02

申请号：US13286843

申请日：2011-11-01

申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.

摘要翻译： 用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。 电流镜电路具有至少两个平行电流路径。 每个电流路径由运算放大器的输出控制。 电流路径之一耦合到运算放大器的两个输入之一。 电阻分压电路连接到另一个电流通路。 电阻分压电路提供电路的带隙电压。

公开(公告)号：US08270213B2

公开(公告)日：2012-09-18

申请号：US12962343

申请日：2010-12-07

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/12

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US08072815B2

公开(公告)日：2011-12-06

申请号：US12965504

申请日：2010-12-10

申请人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C5/025 ,  G11C7/14 ,  G11C16/30 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

摘要翻译： 存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。 每个存储单元连接到位线，高电压源和低电压源。 基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。 高压解码器位于第一侧，连接到同一行的存储单元和参考单元。 低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。 感测放大器位于第三侧，连接到存储单元和参考单元。

公开(公告)号：US20110255346A1

公开(公告)日：2011-10-20

申请号：US13172599

申请日：2011-06-29

申请人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

发明人： Hieu Van Tran ,  Sang T. Nguyen ,  Anh Ly ,  Hung Q. Nguyen

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/28 ,  G11C16/08 ,  G11C16/30

摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

摘要翻译： 各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。 可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。 体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。 各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。 电路可以包括在存储器系统中。

公开(公告)号：US20110080790A1

公开(公告)日：2011-04-07

申请号：US12965504

申请日：2010-12-10

申请人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Anh Ly ,  Hung Q. Nguyen ,  Thuan T. Vu

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C5/025 ,  G11C7/14 ,  G11C16/30 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

摘要翻译： 存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。 每个存储单元连接到位线，高电压源和低电压源。 基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。 高压解码器位于第一侧，连接到同一行的存储单元和参考单元。 低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。 感测放大器位于第三侧，连接到存储单元和参考单元。

公开(公告)号：US20110074492A1

公开(公告)日：2011-03-31

申请号：US12569832

申请日：2009-09-29

申请人： Hieu Van Tran ,  Hung Q. Nguyen ,  Thuant T. Vu ,  Anh Ly

发明人： Hieu Van Tran ,  Hung Q. Nguyen ,  Thuant T. Vu ,  Anh Ly

IPC分类号： G05F3/02 ,  H01L29/92

CPC分类号： H02M3/07 ,  G11C5/145

摘要： A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.

摘要翻译： 用于电荷泵电路的新型电容器具有具有平坦表面的基板。 第一电极处于与平面间隔开的第一平面中。 第二电极与第一平面中的第一电极相邻并且与第一电极间隔开并且与其电容耦合。 第三电极处于与第一平面间隔开的第二平面中并与第一电极电容耦合。 第四电极在第二平面中与第三电极相邻并间隔开，并且电容耦合到第三电极并电容耦合到第二电极。 第一和第四电极电连接在一起，第二和第三电极电连接在一起。 另外，公开了圆柱形电极和长壁电极以及电荷泵电容器逐图案填充。 使用上述电容器的电荷泵电路具有多个用于对电容器充电并对电容器进行放电的晶体管，从而增加电荷泵电路的电压。