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    Field programmable gate array utilizing two-terminal non-volatile memory
    1.
    发明授权
    Field programmable gate array utilizing two-terminal non-volatile memory 有权
    采用双端非易失性存储器的现场可编程门阵列

    公开(公告)号：US08674724B2

    公开(公告)日：2014-03-18

    申请号：US13194500

    申请日：2011-07-29

    申请人： Hagop Nazarian ,  Sang Thanh Nguyen ,  Tanmay Kumar

    发明人： Hagop Nazarian ,  Sang Thanh Nguyen ,  Tanmay Kumar

    IPC分类号： H03K19/0944 ,  H03K19/177 ,  G11C11/00

    CPC分类号： H03K19/0013 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/0944 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776

    摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

    摘要翻译： 本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。 作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。 可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。 分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。 所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

    CHARGE PUMP SYSTEMS AND METHODS
    4.
    发明申请
    CHARGE PUMP SYSTEMS AND METHODS 有权
    充电泵系统和方法

    公开(公告)号：US20110169558A1

    公开(公告)日：2011-07-14

    申请号：US13070405

    申请日：2011-03-23

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    IPC分类号： G05F1/10

    CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

    摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

    摘要翻译： 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

    SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
    5.
    发明申请
    SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
    用于低电压高速感应的感应放大器

    公开(公告)号：US20110121863A1

    公开(公告)日：2011-05-26

    申请号：US12972974

    申请日：2010-12-20

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    IPC分类号： G11C7/08 ,  H03F3/45 ,  G11C7/06

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

    摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

    摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

    Fast Voltage Regulators For Charge Pumps
    6.
    发明申请
    Fast Voltage Regulators For Charge Pumps 有权
    用于充电泵的快速稳压器

    公开(公告)号：US20110121799A1

    公开(公告)日：2011-05-26

    申请号：US12987906

    申请日：2011-01-10

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Anh Ly ,  Hung Q. Nguyen ,  Wingfu Aaron Lau ,  Nasrin Jaffari ,  Thuan Trong Vu ,  Vishal Sarin ,  Loc B. Hoang

    IPC分类号： G05F1/46 ,  G05F3/16 ,  G05F3/08

    CPC分类号： H02M3/07 ,  G11C5/145 ,  H02M1/36 ,  H02M1/44 ,  Y10T307/50

    摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

    摘要翻译： 数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。 电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。 之后，升压电路被禁止，使电荷泵产生高电压而不加速。 升压电路可以被连续地使能以升高电压。 升压电路可以是无负载的。 电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。 电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

    METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP
    7.
    发明申请
    METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP 有权
    用于测试闪存芯片连接性的方法和装置

    公开(公告)号：US20100142272A1

    公开(公告)日：2010-06-10

    申请号：US12629302

    申请日：2009-12-02

    申请人： Sang Thanh Nguyen ,  Hieu Van Tran ,  Hung O. Nguyen ,  Phil Klotzkin

    发明人： Sang Thanh Nguyen ,  Hieu Van Tran ,  Hung O. Nguyen ,  Phil Klotzkin

    IPC分类号： G11C16/04 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C2029/3202

    摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

    摘要翻译： 在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。 该测试电路电连接到IC的接合焊盘。 在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。 本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。 然后检索顺序发送的数据并将其与原始数据进行比较。 因此，这些数据集之间的差异突出了IC中的连接问题。