An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector. The simulator includes an asynchronous transfer point extraction unit that extracts an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain that are input through the input part, a simulation unit that calculates a logic circuit output of the semiconductor integrated circuit by performing a simulation in accordance with the circuit description data and the first test vector that are input through the input part, and a second test vector generation unit that generates a second test vector by changing a signal of an asynchronous transfer point of the logic circuit output calculated by the simulation unit in accordance with the asynchronous transfer point extracted by the asynchronous transfer point extraction unit.